OMAP5912_16 Datasheet, PDF (217/270 Pages) Texas Instruments – OMAP5912 Applications Processor

Electrical Specifications
Table 5−12. Sample Timing Calculation of Table 5−10 Parametric Values
Using Constraints Calculated Above (Continued)
DATASHEET VALUES
AUTOMATIC TIMING
(FROM TABLE 5−10)
CALCULATIONS
NO
PARAMETER
DV_DD5 = 1.8 V/2.75 V/3.3 V
DV_DD5 = 1.8 V/2.75 V/3.3 V
UNIT
NOMINAL
NOMINAL
MIN
MAX
MIN
MAX
FLASH.CS0
Delay time,
Sync modes
F36
t_d(CSV-CLKV)
FLASH.CSx low
to FLASH.CLK
FLASH.CS1,
FLASH.CS2,
high
FLASH.CS3
Sync modes
H − 9.3
H − 8.1
1.12
ns
2.32
ns
Delay time,
F37
t_{d(CLKIV-CSIV)}
FLASH.CLK
invalid to
Sync modes
FLASH.CSx high
H + 0.1
10.52
ns
F40 t_d(OEV-DIV)
Delay time,
FLASH.OE low to
data bus invalid
Async and sync
modes
−4.8
0.64
−4.8
0.64 ns
F41 t_d(OEV-DHZ)
Delay time,
FLASH.OE low to
data bus high Z
Async and sync
modes
−8.9
0.5
−8.9
0.5 ns
F42 t_d(WEV-DIV)
Delay time,
FLASH.WE low
to data bus
invalid
Async and sync
modes
−4.5
1.93
−4.5
1.93 ns
F43 t_d(WEV-DV)
Delay time,
FLASH.WE low
to data bus valid
Async and sync
modes
−4.5
1.93
−4.5
1.93 ns
† _{The maximum EMIFS/flash clock rate is limited to the maximum traffic controller clock rate for the OMAP5912, provided all EMIFS/flash timing}
constraints are met.
‡ _{See Section 5.7.1.1 for information on and an example of how to calculate OMAP5912 EMIFS NOR Flash timings.}
A = (RDWST + 2) * EMIFS clock period (REF_CLK)
B = (ADVHOLD + 1) * EMIFS clock period (REF_CLK)
C = (RDWST – OEHOLD +2) * EMIFS clock period (REF_CLK)
D = (PGWST + 1) * EMIFS clock period (REF_CLK)
E = (WRWST + WELEN + 3) * EMIFS clock period (REF_CLK)
F = (WRWST + 1) * EMIFS clock period (REF_CLK)
G = (WELEN + 1) * EMIFS clock period (REF_CLK)
H = 1 * EMIFS clock period (REF_CLK)
I = 0.5 * EMIFS clock period (REF_CLK)
J = (BTWST + 1) * EMIFS clock period (REF_CLK)
K = OESETUP * EMIFS clock period (REF_CLK)
L = OEHOLD * EMIFS clock period (REF_CLK)
M = (ADVHOLD + 1) * EMIFS clock period (REF_CLK) + 1 TC_CK period
December 2003 − Revised December 2005
SPRS231E 217