OMAP-L138_16 Datasheet, PDF (243/286 Pages) Texas Instruments – OMAP-L138 C6000 DSP ARM Processor

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OMAP-L138
SPRS586I – JUNE 2009 – REVISED SEPTEMBER 2014
Table 6-120. Video Port Interface (VPIF) Registers (continued)
BYTE ADDRESS
0x01E1 70B0
0x01E1 70B4
0x01E1 70B8
0x01E1 70BC
0x01E1 70C0
0x01E1 70C4
0x01E1 70C8
0x01E1 70CC
0x01E1 70D0
0x01E1 70D4
0x01E1 70D8
0x01E1 70DC
0x01E1 70E0
0x01E1 70E4
0x01E1 70E8
0x01E1 70EC
0x01E1 70F0
0x01E1 70F4
0x01E1 70F8
0x01E1 70FC
0x01E1 7100
0x01E1 7104
0x01E1 7108
0x01E1 710C
0x01E1 7110
0x01E1 7114
0x01E1 7118
0x01E1 711C
0x01E1 7120 - 0x01E1 713F
0x01E1 7140
0x01E1 7144
0x01E1 7148
0x01E1 714C
0x01E1 7150
0x01E1 7154
0x01E1 7158
0x01E1 715C
0x01E1 7160
0x01E1 7164
0x01E1 7168
0x01E1 716C
0x01E1 7170
0x01E1 7174
0x01E1 7178
0x01E1 717C
ACRONYM
REGISTER DESCRIPTION
CH1_VSIZE_CFG0
Channel 1 vertical data size configuration (0)
CH1_VSIZE_CFG1
Channel 1 vertical data size configuration (1)
CH1_VSIZE_CFG2
Channel 1 vertical data size configuration (2)
CH1_VSIZE
Channel 1 vertical image size
DISPLAY CHANNEL 2 REGISTERS
CH2_TY_STRTADR
Channel 2 Top Field luma buffer start address
CH2_BY_STRTADR
Channel 2 Bottom Field luma buffer start address
CH2_TC_STRTADR
Channel 2 Top Field chroma buffer start address
CH2_BC_STRTADR
Channel 2 Bottom Field chroma buffer start address
CH2_THA_STRTADR Channel 2 Top Field horizontal ancillary data buffer start address
CH2_BHA_STRTADR Channel 2 Bottom Field horizontal ancillary data buffer start address
CH2_TVA_STRTADR
Channel 2 Top Field vertical ancillary data buffer start address
CH2_BVA_STRTADR Channel 2 Bottom Field vertical ancillary data buffer start address
CH2_SUBPIC_CFG
Channel 2 sub-picture configuration
CH2_IMG_ADD_OFST Channel 2 image data address offset
CH2_HA_ADD_OFST Channel 2 horizontal ancillary data address offset
CH2_HSIZE_CFG
Channel 2 horizontal data size configuration
CH2_VSIZE_CFG0
Channel 2 vertical data size configuration (0)
CH2_VSIZE_CFG1
Channel 2 vertical data size configuration (1)
CH2_VSIZE_CFG2
Channel 2 vertical data size configuration (2)
CH2_VSIZE
Channel 2 vertical image size
CH2_THA_STRTPOS Channel 2 Top Field horizontal ancillary data insertion start position
CH2_THA_SIZE
Channel 2 Top Field horizontal ancillary data size
CH2_BHA_STRTPOS Channel 2 Bottom Field horizontal ancillary data insertion start position
CH2_BHA_SIZE
Channel 2 Bottom Field horizontal ancillary data size
CH2_TVA_STRTPOS
Channel 2 Top Field vertical ancillary data insertion start position
CH2_TVA_SIZE
Channel 2 Top Field vertical ancillary data size
CH2_BVA_STRTPOS Channel 2 Bottom Field vertical ancillary data insertion start position
CH2_BVA_SIZE
Channel 2 Bottom Field vertical ancillary data size
-
Reserved
DISPLAY CHANNEL 3 REGISTERS
CH3_TY_STRTADR
Channel 3 Field 0 luma buffer start address
CH3_BY_STRTADR
Channel 3 Field 1 luma buffer start address
CH3_TC_STRTADR
Channel 3 Field 0 chroma buffer start address
CH3_BC_STRTADR
Channel 3 Field 1 chroma buffer start address
CH3_THA_STRTADR Channel 3 Field 0 horizontal ancillary data buffer start address
CH3_BHA_STRTADR Channel 3 Field 1 horizontal ancillary data buffer start address
CH3_TVA_STRTADR
Channel 3 Field 0 vertical ancillary data buffer start address
CH3_BVA_STRTADR Channel 3 Field 1 vertical ancillary data buffer start address
CH3_SUBPIC_CFG
Channel 3 sub-picture configuration
CH3_IMG_ADD_OFST Channel 3 image data address offset
CH3_HA_ADD_OFST Channel 3 horizontal ancillary data address offset
CH3_HSIZE_CFG
Channel 3 horizontal data size configuration
CH3_VSIZE_CFG0
Channel 3 vertical data size configuration (0)
CH3_VSIZE_CFG1
Channel 3 vertical data size configuration (1)
CH3_VSIZE_CFG2
Channel 3 vertical data size configuration (2)
CH3_VSIZE
Channel 3 vertical image size
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Peripheral Information and Electrical Specifications 243
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