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OMAP-L138_16 Datasheet, PDF (1/286 Pages) Texas Instruments – OMAP-L138 C6000 DSP ARM Processor | |||
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OMAP-L138
SPRS586I â JUNE 2009 â REVISED SEPTEMBER 2014
OMAP-L138 C6000⢠DSP+ ARM® Processor
1 OMAP-L138 C6000 DSP+ARM Processor
1.1 Features
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⢠Dual-Core SoC
â 375- and 456-MHz ARM926EJ-S⢠RISC MPU
â 375- and 456-MHz C674x Fixed- and Floating-
Point VLIW DSP
⢠ARM926EJ-S Core
â 32- and 16-Bit ( Thumb®) Instructions
â DSP Instruction Extensions
â Single-Cycle MAC
â ARM Jazelle® Technology
â Embedded ICE-RT⢠for Real-Time Debug
⢠ARM9⢠Memory Architecture
â 16KB of Instruction Cache
â 16KB of Data Cache
â 8KB of RAM (Vector Table)
â 64KB of ROM
⢠C674x Instruction Set Features
â Superset of the C67x+ and C64x+ ISAs
â Up to 3648 MIPS and 2746 MFLOPS
â Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
â 8-Bit Overflow Protection
â Bit-Field Extract, Set, Clear
â Normalization, Saturation, Bit-Counting
â Compact 16-Bit Instructions
⢠C674x Two-Level Cache Memory Architecture
â 32KB of L1P Program RAM/Cache
â 32KB of L1D Data RAM/Cache
â 256KB of L2 Unified Mapped RAM/Cache
â Flexible RAM/Cache Partition (L1 and L2)
⢠Enhanced Direct Memory Access Controller 3
(EDMA3):
â 2 Channel Controllers
â 3 Transfer Controllers
â 64 Independent DMA Channels
â 16 Quick DMA Channels
â Programmable Transfer Burst Size
⢠TMS320C674x Floating-Point VLIW DSP Core
â Load-Store Architecture with Nonaligned
Support
â 64 General-Purpose Registers (32-Bit)
â Six ALU (32- and 40-Bit) Functional Units
⢠Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
⢠Supports up to Four SP Additions Per Clock,
Four DP Additions Every Two Clocks
⢠Supports up to Two Floating-Point (SP or
DP) Reciprocal Approximation (RCPxP) and
Square-Root Reciprocal Approximation
(RSQRxP) Operations Per Cycle
â Two Multiply Functional Units:
⢠Mixed-Precision IEEE Floating-Point Multiply
Supported up to:
â 2 SP x SP â SP Per Clock
â 2 SP x SP â DP Every Two Clocks
â 2 SP x DP â DP Every Three Clocks
â 2 DP x DP â DP Every Four Clocks
⢠Fixed-Point Multiply Supports Two 32 x 32-
Bit Multiplies, Four 16 x 16-Bit Multiplies, or
Eight 8 x 8-Bit Multiplies per Clock Cycle,
and Complex Multiples
â Instruction Packing Reduces Code Size
â All Instructions Conditional
â Hardware Support for Modulo Loop Operation
â Protected Mode Operation
â Exceptions Support for Error Detection and
Program Redirection
⢠Software Support
â TI DSP BIOSâ¢
â Chip Support Library and DSP Library
⢠128KB of RAM Shared Memory
⢠1.8-V or 3.3-V LVCMOS I/Os (Except for USB and
DDR2 Interfaces)
⢠Two External Memory Interfaces:
â EMIFA
⢠NOR (8- or 16-Bit-Wide Data)
⢠NAND (8- or 16-Bit-Wide Data)
⢠16-Bit SDRAM with 128-MB Address Space
â DDR2/Mobile DDR Memory Controller with one
of the following:
⢠16-Bit DDR2 SDRAM with 256-MB Address
Space
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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