OMAP-L138_16 Datasheet, PDF (177/286 Pages) Texas Instruments – OMAP-L138 C6000 DSP ARM Processor

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OMAP-L138
SPRS586I – JUNE 2009 – REVISED SEPTEMBER 2014
Table 6-76. Additional SPI0 Slave Timings, 4-Pin Chip Select Option ^(1)(2)(3)
NO.
PARAMETER
1.3V, 1.2V
MIN
MAX
25 t_{d(SCSL_SPC)S}
Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge
at slave.
P + 1.5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5M+P+4
26 t_{d(SPC_SCSH)S}
Required delay from final SPI0_CLK edge
before SPI0_SCS is deasserted.
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
P+4
0.5M+P+4
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+4
27 t_{ena(SCSL_SOMI)S} Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid
28 t_{dis(SCSH_SOMI)S} Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI
P+17.5
P+17.5
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-71).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
1.1V
MIN
MAX
P + 1.5
0.5M+P+4
P+4
0.5M+P+4
P+4
P+20
P+20
1.0V
MIN
MAX
P + 1.5
0.5M+P+5
P+5
0.5M+P+5
P+5
P+27
P+27
UNIT
ns
ns
ns
ns
Table 6-77. Additional SPI0 Slave Timings, 5-Pin Option ^(1)(2)(3)
NO.
PARAMETER
25 t_{d(SCSL_SPC)S}
26 t_{d(SPC_SCSH)S}
27 t_{ena(SCSL_SOMI)S}
28 t_{dis(SCSH_SOMI)S}
29 t_{ena(SCSL_ENA)S}
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
Required delay from final
from SPI0_CLK falling
SPI0_CLK edge before SPI0_SCS
is deasserted.
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
Delay from master deasserting SPI0_SCS to slave driving
SPI0_ENA valid
1.3V, 1.2V
MIN
MAX
P + 1.5
0.5M+P+4
P+4
0.5M+P+4
P+4
P+17.5
P+17.5
17.5
1.1V
MIN
MAX
P + 1.5
0.5M+P+4
P+4
0.5M+P+4
P+4
P+20
P+20
20
1.0V
MIN
MAX
P + 1.5
0.5M+P+5
P+5
0.5M+P+5
P+5
P+27
P+27
27
UNIT
ns
ns
ns
ns
ns
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-71).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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