BQ24140_14 Datasheet, PDF (23/39 Pages) Texas Instruments – Integrated Dual-Input Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support

bq24140
www.ti.com
SLUSAO5 – OCTOBER 2011
Safety Limit Registers
The bq24140 includes safety limit registers which are used as an extra level of security for devices that allow
applications to be developed by third party vendors (i.e. Android OS). The purpose of the safety limit registers is
to program the maximum allowable battery regulation voltage and charge current. These two registers need to be
written before any other write actions are sent to the bq24140. Once a write action to a register other than the
safety limit registers, the values on the safety limit registers will be locked.
SLRST Pin
When SLRST=0, the bq24140 will reset all the safety limits to default values, regardless of the write actions to
safety limits registers (06H). When SLRST=1, the bq24140 can program the safety limit register until any write
action to other registers locks the programmed safety limits.
VREG LDO
The bq24140 includes a 2.6V LDO that can be used as an indication of the VIN input being connected. This LDO
is active all the time when there is a power source connected to the VIN input. The current limit on the LDO
guarantees up to 10mA.
SERIAL INTERFACE DESCRIPTION
I²C is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I²C compatible devices connect to the I2C bus
through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The IC works as a slave and is compatible with the following data transfer modes, as defined in the I²C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4 Mbps in write
mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements. Register contents remain intact as long as
supply voltage remains above 2.2 V (typical). I²C is asynchronous, which means that it runs off of SCL. The
device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is recommended that
SDA changes while SCL is LOW.
The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to
as HS-mode. The IC supports 7-bit addressing only. The device has two 7-bit addresses, defined as
‘1101011’ (6BH) for USB portion and, and ‘1101010’ (6AH) for AC portion.
Copyright © 2011, Texas Instruments Incorporated
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