BQ24140_14 Datasheet, PDF (2/39 Pages) Texas Instruments – Integrated Dual-Input Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support

bq24140
SLUSAO5 – OCTOBER 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The bq24140 is a compact, flexible, high-efficiency, USB-friendly switch-mode charge management device for
single-cell Li-ion and Li-polymer batteries used in a wide range of portable applications. The charge parameters
can be programmed through an I²C interface. The IC integrates two synchronous PWM chargers, power
MOSFETs, input current sensing, high-accuracy current and voltage regulation, and charge termination, into a
small WCSP package.
The IC charges the battery in three phases: conditioning, constant current and constant voltage. The input
current is automatically limited to the value set by the host. Charge is terminated based on user-selectable
minimum current level. A safety timer with reset control provides a safety backup for I²C interface. During normal
operation, the IC automatically restarts the charge cycle if the battery voltage falls below an internal threshold
and automatically enters sleep mode or high impedance mode when the input supply is removed. The charge
status can be reported to the host using the I²C interface. During the charging process, the IC monitors its
junction temperature (T_J) and reduces the charge current once T_J increases to 125°C typical. To support USB
OTG device, the IC can provide VBUS (5.05V typical) by boosting the battery voltage. The IC is available in
30-pin WCSP package.
DEVICE INFORMATION
PIN OUT (TOP VIEW)
1
2
3
4
5
A BOOT VREF VREG SDA BOOT1
B
VIN
VIN
SCL VBUS VBUS
C _{PMID2 PMID2 SLRST PMID1 PMID1}
D
SW2 SW2
DIS
SW1
SW1
E
GND
GND
GND
GND
GND
F
LED
OTG CSIN VBAT STAT
PIN
NAME
NO.
BOOT
A1
VREF
A2
VREG
A3
SDA
A4
BOOT1
A5
VIN
B1 – B2
SCL
B3
VBUS
B4 – B5
PMID2 C1 – C2
PIN FUNCTIONS
I/O
DESCRIPTION
O
Boot-strapped capacitor for the high-side MOSFET gate driver. Connect a 100nF ceramic capacitor (voltage
rating above 10V) from BOOT pin to SW2 pin.
O Internal bias regulator voltage. Connect a 1µF ceramic capacitor from this output to PGND.
O Voltage regulator. 2.5V with 10mA current capability. Connect a 0.1μF ceramic capacitor to ground
I/O I2C interface data. Connect a 10-kΩ pull-up resistor to 1.8V rail.
O
Boot-strapped capacitor for the high-side MOSFET gate driver. Connect a 100nF ceramic capacitor (voltage
rating above 10V) from BOOT1 pin to SW1 pin.
I Charger input voltage. Bypass it with a 1μF ceramic capacitor from VIN to GND.
I I²C interface clock. Connect a 10-kΩ pull-up resistor to 1.8V rail.
I/O
Charger input voltage. Bypass it with a 4.7μF ceramic capacitor from VBUS to GND. This pin also provides the
output of the boost converter when in Boost Mode.
O
Connection point between reverse blocking FET and high-side switching FET. Bypass it with a minimum of
3.3μF capacitor from PMID2 to GND.
2
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