BQ25872 Datasheet, PDF (20/68 Pages) Texas Instruments – Battery Switch Charger

bq25872
SLUSCQ6 – OCTOBER 2016
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Feature Description (continued)
FET gate capacitance) and does not depend on the EN pin status (i.e., feature is always active as long as V_VUSB
> VUSB_PRESENT). If the EN pin is pulled high, then I²C communication to the device is available, and the OVP
threshold can then be changed via the VUSBOVP_I2C bits. The final VUSB OVP threshold is set by the lower
setting of the OVPSET pin and the VUSBOVP_I2C bits. VUSBOVP_I2C bits are not reset when EN is asserted
low and are only reset by REG_RST or a POR event.
8.3.5.3.1 OVPSET pin
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
The default power up OVP threshold can be set via the OVPSET pin with a single external resistor to one of
three preset thresholds – 6.5 V, 10.5 V, and 14 V. The OVPSET pin will source a current to determine the
resistance on the pin, and then set the OVP threshold accordingly. The OVPSET pin will follow these threshold
assignments:
• Highest pin threshold (floating) = 6.5-V OVP threshold
• Lowest pin threshold (tied to GND) = 14.5-V OVP threshold
• Mid-point pin threshold (22 kΩ to GND) = 10.5 V
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