BQ2022A_17 Datasheet, PDF (20/37 Pages) Texas Instruments – 1K-Bit Serial EPROM with SDQ Interface

bq2022A
SLUS724E – SEPTEMBER 2006 – REVISED MARCH 2016
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8.2.2 Detailed Design Procedure
8.2.2.1 Programming Circuit Example
The bq2022A requires a 12-V maximum pulse signal to program the OTP memory. It is necessary to have a
programming test setup for production. Figure 19 shows an example of what the circuit could be for such setup.
The Programming Module contains the microcontroller that acts as SDQ master and also controls the time of the
programming pulse and its width. The 12-V supply is the source for the programming pulse. Only SDQ and VSS
signals need to exit the test setup as the Application Circuit containing the bq2022A under test is connected only
for programming and verifying data.
The Programming Module typically will connect to a PC using interface such as USB. The diagram in Figure 19
does not include the interface to a PC which can vary depending on the system designer's choice.
Programming Module
12V Supply
10NŸ
15NŸ
µController
3.3V
10NŸ
100Ÿ
100Ÿ
5.6V
Application Circuit
bq2022A
SDQ
VSS
Figure 19. bq2022A Programming Circuit Example
8.2.2.2 SDQ Master Best Practices
It may be necessary to “bit-bang” a GPIO on the host system to act as the SDQ master. In this case, some
additional error checking should be built into the code used to reset the bq2022A to ensure that the slave is
operating as expected on the bus.
Whenever the host sends a reset, the bq2022A responds with a presence pulse. The host should confirm, before
the presence pulse, that the bus has been released and returned to a high level, indicating that nothing is holding
the bus unexpectedly low. As the minimum t_ppd is 15 µs, having the host look for a logic high on the bus 10 µs
after releasing the bus at the end of the reset is sufficient to confirm the bus is released for the bq2022A to
respond.
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