BQ2022A_17 Datasheet, PDF(15/37 Page) Texas Instruments – 1K-Bit Serial EPROM with SDQ Interface

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BQ2022A_17 Datasheet, PDF (15/37 Pages) Texas Instruments – 1K-Bit Serial EPROM with SDQ Interface

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bq2022A

SLUS724E â SEPTEMBER 2006 â REVISED MARCH 2016

After the programming pulse is applied and the data line returns to VPU, the host issues eight read time slots to

verify that the appropriate bits have been programmed. The bq2022A responds with the data from the selected

EPROM STATUS address sent least significant bit first. This response should be checked to verify the

programmed byte. If the programmed byte is incorrect, then the host must reset the device and begin the write

sequence again. If the bq2022A EPROM data byte programming was successful, the bq2022A automatically

increments its address counter to select the next byte in the STATUS MEMORY data field. The least significant

byte of the new two-byte address is also loaded into the 8-bit CRC generator as a starting value. The host issues

the next byte of data using eight write time slots.

As the bq2022A receives this byte of data into the RAM buffer, it also shifts the data into the CRC generator that

has been preloaded with the LSB of the current address and the result is an 8-bit CRC of the new data byte and

the LSB of the new address. After supplying the data byte, the host reads this 8-bit CRC from the bq2022A with

eight read time slots to confirm that the address incremented properly and the data byte was received correctly.

If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be

restarted. If the CRC is correct, the host issues a programming pulse and the selected byte in memory is

programmed.

NOTE

The initial write of the WRITE STATUS command, generates an 8-bit CRC value that is

the result of shifting the command byte into the CRC generator, followed by the two-

address bytes, and finally the data byte. Subsequent writes within this WRITE STATUS

command due to the bq2022A automatically incrementing its address counter generates

an 8-bit CRC that is the result of loading (not shifting) the LSB of the new (incremented)

address into the CRC generator and then shifting in the new data byte.

For both of these cases, the decision to continue programming the EPROM Status registers is made entirely by

the host, because the bq2022A is not able to determine if the 8-bit CRC calculated by the host agrees with the 8-

bit CRC calculated by the bq2022A. If an incorrect CRC is ignored and a program pulse is applied by the host,

incorrect programming could occur within the bq2022A. Also note that the bq2022A always increments its

internal address counter after the receipt of the eight read time slots used to confirm the programming of the

selected EPROM byte. The decision to continue is again made entirely by the host, therefore if the EPROM data

byte does not match the supplied data byte but the master continues with the WRITE STATUS command,

incorrect programming could occur within the bq2022A. The WRITE STATUS command sequence can be ended

at any point by issuing a reset pulse.

Table 3. Command Code Summary

COMMAND

(HEX)

33h

CCh

F0h

AAh

C3h

0Fh

99h

55h

DESCRIPTION

Read Serialization ROM and

CRC

Skip Serialization ROM

Read Memory/Field CRC

Read EPROM Status

Read Memory/Page CRC

Write Memory

Programming Profile

Write EPROM Status

5Ah

Program Control