BQ2022A_17 Datasheet, PDF (16/37 Pages) Texas Instruments – 1K-Bit Serial EPROM with SDQ Interface

bq2022A
SLUS724E – SEPTEMBER 2006 – REVISED MARCH 2016
www.ti.com
From SKIP
ROM
Command
Program
N
Profile Command?
99h
Y
bq2022 Transmits
55h
Other
Command
Codes
Master Issues Reset
bq2022A
is in
Reset State
Figure 12. PROGRAM PROFILE Command Flow
7.5.10 SDQ Signaling
All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or
to begin the start frame for a bit read. Figure 13 shows the initialization timing, whereas Figure 14 and Figure 15
show that the host initiates each bit by driving the DATA bus low for the start period, t_WSTRB / t_RSTRB. After the bit
is initiated, either the host continues controlling the bus during a WRITE, or the bq2022A responds during a
READ.
7.5.11 RESET and PRESENCE PULSE
If the DATA bus is driven low for more than 120 μs, the bq2022A may be reset. Figure 13 shows that if the DATA
bus is driven low for more than 480 μs, the bq2022A resets and indicates that it is ready by responding with a
PRESENCE PULSE.
V_PU
V_IH
V_IL
RESET
(Sent by Host)
Presence Pulse
(Sent by bq2022A)
t_RST
t_PPD
t_PP
t_RSTREC
Figure 13. Reset Timing Diagram
7.5.12 WRITE Bit
The WRITE bit timing diagram in Figure 14 shows that the host initiates the transmission by issuing the t_WSTRB
portion of the bit and then either driving the DATA bus low for a WRITE 0, or releasing the DATA bus for a
WRITE 1.
VPU _VIH
V _IL
Write ”1”
Write ”0”
t _WSTRB
t _rec
t _WDSU
t _WDH
Figure 14. WRITE Bit Timing Diagram
16
Submit Documentation Feedback
Product Folder Links: bq2022A
Copyright © 2006–2016, Texas Instruments Incorporated