BQ2022A_17 Datasheet, PDF (10/37 Pages) Texas Instruments – 1K-Bit Serial EPROM with SDQ Interface

bq2022A
SLUS724E – SEPTEMBER 2006 – REVISED MARCH 2016
www.ti.com
Programming (continued)
7.5.5 READ MEMORY Commands
Two READ MEMORY commands are available on the bq2022A. Both commands are used to read data from the
1024-bit EPROM data field. They are the READ MEMORY/Page CRC and the READ MEMORY/Field CRC
commands. The READ MEMORY/Page CRC generates CRC at the end any 32-byte page boundary whereas
the READ MEMORY/Field CRC generates CRC when the end of the 1024-bit data memory is reached.
7.5.5.1 READ MEMORY/Page CRC
To read memory and generate the CRC at the 32-byte page boundaries of the bq2022A, the SKIP ROM
command is followed by the READ MEMORY/Generate CRC command, C3h, followed by the address low byte
and then the address high byte.
An 8-bit CRC of the command byte and address bytes is computed by the bq2022A and read back by the host to
confirm that the correct command word and starting address were received. If the CRC read by the host is
incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the
host is correct, the host issues read time slots and receives data from the bq2022A starting at the initial address
and continuing until the end of a 32-byte page is reached. At that point, the host sends eight additional read time
slots and receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the
initial starting byte to the last byte of the current page. Once the 8-bit CRC has been received, data is again read
from the 1024-bit EPROM data field starting at the next page. This sequence continues until the final page and
its accompanying CRC are read by the host. Thus each page of data can be considered to be 33 bytes long, the
32 bytes of user-programmed EPROM data and an 8-bit CRC that gets generated automatically at the end of
each page.
Initialization and SKIP
ROM Command
Sequence
READ
MEMORY/Generate
CRC Command
Address Low Byte
Address High
Byte
Read and
Verify CRC
C3h
A0
A7 A8
A15
NOTE: Individual bytes of address and data are transmitted LSB first.
Figure 7. READ MEMORY/Page CRC
EPROM Memory and
CRC Byte
Generated at 32-Byte
Page
Boundaries
7.5.5.2 READ MEMORY/Field CRC
To read memory without CRC generation on 32-byte page boundaries, the SKIP ROM command is followed by
the READ MEMORY command, F0h, followed by the address low byte and then the address high byte.
NOTE
As shown in Figure 8, individual bytes of address and data are transmitted LSB first.
An 8-bit CRC of the command byte and address bytes is computed by the bq2022A and read back by the host to
confirm that the correct command word and starting address were received. If the CRC read by the host is
incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the
host is correct, the host issues read time slots and receives data from the bq2022A starting at the initial address
and continuing until the end of the 1024-bit data field is reached or until a reset pulse is issued. If reading occurs
through the end of memory space, the host may issue eight additional read time slots and the bq2022A responds
with an 8-bit CRC of all data bytes read from the initial starting byte through the last byte of memory. After the
CRC is received by the host, any subsequent read time slots appear as logical 1s until a reset pulse is issued.
Any reads ended by a reset pulse prior to reaching the end of memory does not have the 8-bit CRC available.
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