TLC34077 Datasheet, PDF (19/41 Pages) Texas Instruments – Video Interface Palette Data Manual

Table 2–6. True-Color Mode
MODE
MUX CONTROL REGISTER BITS†
DATA
BITS PER
PIXEL‡
PIXEL
BUS
WIDTH
LCLK
DIVIDE
RATIO§
OVERLAY
BITS PER
PIXEL (4)
PIXEL
LATCHING
SEQUENCE¶
543210
3
3a
001000
15
16
1
3b
001001
16
16
1
3c
001010
15
32
2
1
1) P<15:0>
N/A
1) P<15:0>
1) P<15:0>
1
2) P<31:16>
3d
001011
16
32
2
N/A
1) P<15:0>
2) P<31:16>
3e
001110
24
32
1
3f
001101
24
32
1
8
1) P<31:0>
8
1) P<31:0>
† _{Bits 6 and 7 are don’t care bits.}
‡ _{This is the number of bits of pixel port (or VGA port in mode 1) information used as color data for each displayed pixel,}
often referred to as the number of bit planes. This may be color palette address data (Modes 0 – 2) or DAC data
(Mode 3).
§ _{The LCLK divide ratio is the number used for the output clock selection register. It indicates the number of pixels per}
bus load or the number of pixels associated with each LCLK pulse. For example, with a 16-bit pixel bus width and 8 bit
planes, 2 pixels comprise each bus load. The LCLK divide ratio is not automatically set by mode selection, but must
be written to the output clock selection register.
¶ _{For each operating mode, the pixel latching sequence indicates the sequence in which pixel port or VGA port data are}
latched into the device. The latching sequence is initiated by a rising edge on LCLK. For modes in which multiple groups
of data are latched, the LCLK rising edge latches all the groups, and the pixel clock shifts them out starting with the
low-numbered group. For example, in mode 6d with a 32-bit pixel bus width, the rising edge of LCLK latches all the data
groups, and the pixel clock shifts them out in the order P<15:0>, P<31:16>.
|| _{For proper true color operation, all overlay bits defined for a given true color mode must be set to logic 0 or the read mask}
must be cleared by setting it to 00h. See Table 2–7.
NOTE: Although leaving unused pins floating will not adversely affect device operation, tying unused pins to ground
lowers power consumption and, thus, is recommended.
Table 2–7. True-Color Bit Definitions
Little Endian
Pixel Bus P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16
Data Bus D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
a
b
c
O R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
d
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
e
O7 O6 O5 O4 O3 O2 O1 O0 R7 R6 R5 R4 R3 R2 R1 R0
f
B7 B6 B5 B4 B3 B2 B1 B0 G7 G6 G5 G4 G3 G2 G1 G0
Pixel Bus P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
Data Bus D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
a
O R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
b
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
c
O R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
d
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
2-7