TLC34077 Datasheet, PDF (11/41 Pages) Texas Instruments – Video Interface Palette Data Manual

PIN
I/O
NAME
NO.
DESCRIPTION
VGA<0:7>
65 – 72
I VGA pass-through bus. This bus can be selected as the pixel bus for VGA
pass-through mode. It does not allow for any multiplexing.
VREF
53
Voltage reference for DACs. (An internal voltage reference of nominally
1.235 V is supplied in.) A 0.1-µF ceramic capacitor between this terminal and
GND is recommended for noise filtering using either the internal or an
external reference voltage. The internal reference voltage can be overridden
by an externally supplied voltage. The typical connection is shown in
Appendix B.
WR
30
I Write strobe input. A low logic level on this pin initiates a write to the
TLC34077 register map. Write transfers are asynchronous. The data written
to the register map is latched on the rising edge of WR (see Figure 3–1).
8/6
64
I DAC resolution selection. This pin is used to select the data bus width (8 or
6 bits) for the DACs and is provided to maintain compatibility with the INMOS
IMSG176/8 color palette. When this pin is at a high logic level, 8-bit bus
transfers are used, with D<7> being the MSB and D<0> the LSB. For 6-bit
bus operation, while the color palette still has the 8-bit information, D<5>
shifts to the bit 7 position, D<0> shifts to the bit 2 position, and the two LSBs
are filled with zeros at the output MUX to the DAC. When read in the 6-bit
mode, the palette-holding register zeroes out the two MSBs.
NOTES: 1. Although leaving unused pins floating will not adversely affect device operation, tying unused pins to ground
lowers power consumption and, thus, is recommended.
2. All digital inputs and outputs are TTL compatible, unless otherwise noted.
1-5