TLC34077 Datasheet, PDF (18/41 Pages) Texas Instruments – Video Interface Palette Data Manual

by the overlay input, is still governed by 8/6-input pin and the output MUX will select 8-bits data or 6-bits data
accordingly. The 8/6-input pin is also valid in the other 16-bit modes as well.
2.4.4 Multiplex Control Register
The multiplexer is controlled via the 8-bit multiplex control register. The bit fields of the register are in
Table 2– 5 and Table 2–6.
As an example of how to use Table 2– 5, suppose that the design goals specify a system with eight data bits
per pixel and the lowest possible LCLK rate. Table 2– 5 shows that, for non-VGA-pass-through operation,
Modes 1 and 2 support an 8-bit pixel depth. The lowest-possible LCLK rate within mode 1 is 1:2. This set
of conditions is selected by writing the value 10h to the mux control register. The pixel latching sequence
column shows that, in this mode, P<7:0> should be connected to the earliest-displayed pixel plane, followed
by P<15:8>, as the last displayed pixel plane. Assuming that VCLK is programmed as DOTCLK/2,
Table 2– 4 shows that the 1:2 LCLK ratio is selected by writing the value 09h to the output clock selection
register.
When the mux control register is loaded with 2Dh, the TLC34077 enters the VGA pass-through mode (the
same condition as the default power-up mode). Please refer to Section 2.5.4 for more details.
Table 2–5. Mode and Bus Width Selection
MODE
MUX CONTROL REGISTER BITS†
DATA BITS
PER
PIXEL‡
PIXEL BUS
WIDTH
LCLK
DIVIDE
RATIO§
PIXEL
LATCHING
SEQUENCE¶
5
4
3
2
1
0
0#
1
0
1
1
0
1
8
8
1
1) VGA<7:0>
1
0
1
1
1
0
0
8
8
1
1) P<7:0>
2
0
1
1
1
0
1
8
16
2
1) P<7:0>
2) P<15:8>
3
See Table 2–6 and Table 2–7
† _{Bits 6 and 7 are don’t care bits.}
‡ _{This is the number of bits of pixel port (or VGA port in mode 1) information used as color data for each displayed pixel,}
often referred to as the number of bit planes. This may be color palette address data (Modes 0 – 2) or DAC data
(mode 3).
§ _{The LCLK divide ratio is the number used for the output clock selection register. It indicates the number of pixels per}
bus load or the number of pixels associated with each LCLK pulse. For example, with a 16-bit pixel bus width and 8 bit
planes, 2 pixels comprise each bus load. The LCLK divide ratio is not automatically set by mode selection, but must
be written to the output clock selection register.
¶ _{For each operating mode, the pixel latching sequence indicates the sequence in which pixel port or VGA port data are}
latched into the device. The latching sequence is initiated by a rising edge on LCLK. For modes in which multiple groups
of data are latched, the LCLK rising edge latches all the groups, and the pixel clock shifts them out starting with the
low-numbered group.
# _{Mode 0 is VGA pass-through mode.}
|| _{For proper true color operation, all overlay bits defined for a given true color mode must be set to logic 0 or the read mask}
must be cleared by setting it to 00h. See Table 2–7.
NOTE: Although leaving unused pins floating will not adversely affect device operation, tying unused pins to ground
lowers power consumption and, thus, is recommended.
2-6