TLC34077 Datasheet, PDF (10/41 Pages) Texas Instruments – Video Interface Palette Data Manual

1.5 Terminal Functions
PIN
I/O
NAME
NO.
BLANK,
60, 61
I
VGABLANK
CLK<0:1>
77, 76
I
COMP
52
I
D<0:7>
36 – 43
I/O
FS ADJUST
51
I
GND
44, 54, 56,
80
HSYNC, VSYNC 58, 59
I
IOR, IOG, IOB 48, 49, 50 O
NC
P<0:31>
46, 47, 62,
63, 73, 74,
75, 79
29 –1,
I
84 – 82
RD
31
I
RS<0:3>
VCLK
VDD
32–35
I
78
O
45, 55, 57,
81
DESCRIPTION
Blanking inputs. Two blanking inputs are provided in order to remove any
external multiplexing of the signals that may cause data and blank to skew.
When the VGA pass-through mode is set in the mux control register, the
VGABLANK input is used for blanking; otherwise, BLANK is used.
Dot clock inputs. Any of the three clocks can be used to drive the dot clock
at frequencies up to 135 MHz. When VGA pass-through mode is active,
CLK0 is used by default.
Compensation input. This terminal provides compensation for the internal
reference amplifier. A resistor (optional) and ceramic capacitor are required
between this terminal and VDD. The resistor and capacitor must be as close
to the device as possible to avoid noise pickup. Refer to Appendix B for more
details.
MPU interface data bus. Used to transfer data in and out of the register map
and palette/overlay RAM.
Full-scale adjustment pin. A resistor connected between this pin and ground
controls the full-scale range of the DACs.
Ground. All GND pins must be connected. The analog and digital GND pins
are connected internally.
Horizontal and vertical sync inputs. These signals are used to generate the
sync level on the green current output. They are active-low inputs for the
normal modes and are passed through a true/complement gate. For the VGA
pass-through mode, they are passed through to HSYNCOUT and
VSYNCOUT without polarity change as specified by the control register (see
Section 2.8).
Analog current outputs. These outputs can drive a 37.5-Ω load directly
(doubly terminated 75-Ω line), thus eliminating the need for any external
buffering.
No internal connection
Pixel input port. This port can be used in various modes as shown in the MUX
control register. It is recommended that unused pins be tied to ground. It also
supports Little/Big Endian data formats. All the unused pins must be tied to
GND.
Read strobe input. A low logic level on this pin initiates a read from the
TLC34077 register map. Reads are performed asynchronously and are
initiated on the falling edge of RD (see Figure 3 –1).
Register select inputs. These pins specify the location in the register map
that is to be accessed, as shown in Table 2–1.
Video clock output. User-programmable output for synchronization of the
TLC34077 to a graphics processor.
Power. All VDD pins must be connected. The analog and digital VDD pins are
connected internally.
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