SM74203 Datasheet, PDF(19/24 Page) Texas Instruments – SM74203 60V Low Side Controller for Boost and SEPIC

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SM74203 Datasheet, PDF (19/24 Pages) Texas Instruments – SM74203 60V Low Side Controller for Boost and SEPIC

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PQ = 13.8 X (3.5m + 13.5m) = 235 mW

MOSFET SWITCHING LOSS

PSW = 0.5 x VIN x IL x (tR + tF) x fSW

PSW = 0.5 x 13.8 x 1.5 x (10 ns + 12 ns) x 5 x 105 = 114 mW

MOSFET AND RSNS CONDUCTION LOSS

PC = D x (IL2 x (RDSON x 1.3 + RSNS))

PC = 0.66 x (1.52 x (0.029 + 0.1)) = 192 mW

OUTPUT DIODE LOSS

The average output diode current is equal to IO, or 0.5A. The

estimated forward drop, VD, is 0.5V. The output diode loss is

therefore:

PD1 = IO x VD

PD1 = 0.5 x 0.5 = 0.25W

INPUT CAPACITOR LOSS

This term represents the loss as input ripple current passes

through the ESR of the input capacitor bank. In this equation

ânâ is the number of capacitors in parallel. The 4.7 ÂµF input

capacitors selected have a combined ESR of approximately

1.5 mâ¦, and ÎiL for a 13.8V input is 0.55A:

IIN-RMS = 0.29 x ÎiL = 0.29 x 0.55 = 0.16A

PCIN = [0.162 x 0.0015] / 2 = 0.02 mW (negligible)

OUTPUT CAPACITOR LOSS

This term is calculated using the same method as the input

capacitor loss, substituting the output capacitor RMS current

for VIN = 13.8V. The output capacitors' combined ESR is also

approximately 1.5 mâ¦.

IO-RMS = 1.13 x 1.5 x (0.66 x 0.34)0.5 = 0.8A

PCO = [0.8 x 0.0015] / 2 = 0.6 mW

BOOST INDUCTOR LOSS

The typical DCR of the selected inductor is 40 mâ¦.

PDCR = IL2 x DCR

PDCR = 1.52 x 0.04 = 90 mW

Core loss in the inductor is estimated to be equal to the DCR

loss, adding an additional 90 mW to the total inductor loss.

TOTAL LOSS

PLOSS = Sum of All Loss Terms = 972 mW

EFFICIENCY

Î· = 20 / (20 + 0.972) = 95%

Layout Considerations

To produce an optimal power solution with the SM74203,

good layout and design of the PCB are as important as the

component selection. The following are several guidelines to

aid in creating a good layout.

FILTER CAPACITORS

The low-value ceramic filter capacitors are most effective

when the inductance of the current loops that they filter is

minimized. Place CINX as close as possible to the VIN and

GND pins of the SM74203. Place COX close to the load, and

CF next to the VCC and GND pins of the SM74203.

SENSE LINES

The top of RSNS should be connected to the CS pin with a

separate trace made as short as possible. Route this trace

away from the inductor and the switch node (where D1, Q1,

and L1 connect). For the voltage loop, keep RFB1/2 close to

the SM74203 and run a trace from as close as possible to the

positive side of COX to RFB2. As with the CS line, the FB line

should be routed away from the inductor and the switch node.

These measures minimize the length of high impedance lines

and reduce noise pickup.

COMPACT LAYOUT

Parasitic inductance can be reduced by keeping the power

path components close together and keeping the area of the

loops that high currents travel small. Short, thick traces or

copper pours (shapes) are best. In particular, the switch node

should be just large enough to connect all the components

together without excessive heating from the current it carries.

The SM74203 (boost converter) operates in two distinct cy-

cles whose high current paths are shown in Figure 11:

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FIGURE 11. Boost Converter Current Loops

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