SM74203 Datasheet, PDF (17/24 Pages) Texas Instruments – SM74203 60V Low Side Controller for Boost and SEPIC

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FIGURE 8. Power Stage Gain and Phase
The single pole causes a roll-off in the gain of -20 dB/decade
at lower frequency. The combination of the RHP zero and
sampling double pole maintain the slope out to beyond the
switching frequency. The phase tends towards -90° at lower
frequency but then increases to -180° and beyond from the
RHP zero and the sampling double pole. The effect of the
ESR zero is not seen because its frequency is several
decades above the switching frequency. The combination of
increasing gain and decreasing phase makes converters with
RHP zeroes difficult to compensate. Setting the overall con-
trol loop bandwidth to 1/3 to 1/10 of the RHP zero frequency
minimizes these negative effects, but requires a compromise
in the control loop bandwidth. If this loop were left uncom-
pensated, the bandwidth would be 89 kHz and the phase
margin -54°. The converter would oscillate, and therefore is
compensated using the error amplifier and a few passive
components.
The transfer function of the compensation block, G_EA, can be
derived by treating the error amplifier as an inverting op-amp
with input impedance Z_I and feedback impedance Z_F. The
majority of applications will require a Type II, or two-pole one-
zero amplifier, shown in Figure 7. The LaPlace domain trans-
fer function for this Type II network is given by the following:
Many techniques exist for selecting the compensation com-
ponent values. The following method is based upon setting
the mid-band gain of the error amplifier transfer function first
and then positioning the compensation zero and pole:
1. Determine the desired control loop bandwidth: The
control loop bandwidth, f_0dB, is the point at which the total
control loop gain (H = G_PS x G_EA) is equal to 0 dB. For
this example, a low bandwidth of 10 kHz, or
approximately 1/6th of the RHP zero frequency, is
chosen because of the wide variation in input voltage.
2. Determine the gain of the power stage at f_0dB: This
value, A, can be read graphically from the gain plot of
G_PS or calculated by replacing the ‘s’ terms in G_PS with
‘2πf_0dB’. For this example the gain at 10 kHz is
approximately 16 dB.
3. Calculate the negative of A and convert it to a linear
gain: By setting the mid-band gain of the error amplifier
to the negative of the power stage gain at f_0dB, the control
loop gain will equal 0 dB at that frequency. For this
example, -16 dB = 0.15V/V.
4. Select the resistance of the top feedback divider
resistor R_FB2: This value is arbitrary, however selecting
a resistance between 10 kΩ and 100 kΩ will lead to
practical values of R1, C1 and C2. For this example,
R_FB2 = 20 kΩ 1%.
5. Set R1 = A x R_FB2: For this example: R1 = 0.15 x 20000
= 3 kΩ
6. Select a frequency for the compensation zero, f_Z1:
The suggested placement for this zero is at the low
frequency pole of the power stage, f_LFP = ωLFP / 2π. For
this example, f_Z1 = f_LFP = 423Hz
7. Set
For this example, C2 = 125 nF
8. Select a frequency for the compensation pole, f_P1:
The suggested placement for this pole is at one-fifth of
the switching frequency. For this example, f_P1 = 100 kHz
9. Set
For this example, C1 = 530 pF
10. Plug the closest 1% tolerance values for R_FB2 and R1,
then the closest 10% values for C1 and C2 into G_EA
and model the error amp: The open-loop gain and
bandwidth of the SM74203’s internal error amplifier are
75 dB and 4 MHz, respectively. Their effect on G_EA can
be modeled using the following expression:
A_DC is a linear gain, the linear equivalent of 75 dB is
approximately 5600V/V. C1 = 560 pF 10%, C2 = 120 nF
10%, R1 = 3.01 kΩ 1%
11. Plot or evaluate the actual error amplifier transfer
function:
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