SM74203 Datasheet, PDF (10/24 Pages) Texas Instruments – SM74203 60V Low Side Controller for Boost and SEPIC

To set the switching frequency, f_SW, R_T can be calculated
from:
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FIGURE 2. Enable/Disable Using UVLO
ERROR AMPLIFIER
An internal high gain error amplifier is provided within the
SM74203. The amplifier’s non-inverting input is internally set
to a fixed reference voltage of 1.25V. The inverting input is
connected to the FB pin. In non-isolated applications such as
the boost converter the output voltage, V_O, is connected to
the FB pin through a resistor divider. The control loop com-
pensation components are connected between the COMP
and FB pins. For most isolated applications the error amplifier
function is implemented on the secondary side of the con-
verter and the internal error amplifier is not used. The internal
error amplifier is configured as an open drain output and can
be disabled by connecting the FB pin to ground. An internal
5 kΩ pull-up resistor between a 5V reference and COMP can
be used as the pull-up for an opto-coupler in isolated appli-
cations.
CURRENT SENSING AND CURRENT LIMITING
The SM74203 provides a cycle-by-cycle over current protec-
tion function. Current limit is accomplished by an internal
current sense comparator. If the voltage at the current sense
comparator input exceeds 0.5V, the MOSFET gate drive will
be immediately terminated. A small RC filter, located near the
controller, is recommended to filter noise from the current
sense signal. The CS input has an internal MOSFET which
discharges the CS pin capacitance at the conclusion of every
cycle. The discharge device remains on an additional 65 ns
after the beginning of the new cycle to attenuate leading edge
ringing on the current sense signal.
The SM74203 current sense and PWM comparators are very
fast, and may respond to short duration noise pulses. Layout
considerations are critical for the current sense filter and
sense resistor. The capacitor associated with the CS filter
must be located very close to the device and connected di-
rectly to the pins of the controller (CS and GND). If a current
sense transformer is used, both leads of the transformer sec-
ondary should be routed to the sense resistor and the current
sense filter network. The current sense resistor can be locat-
ed between the source of the primary power MOSFET and
power ground, but it must be a low inductance type. When
designing with a current sense resistor all of the noise sensi-
tive low-power ground connections should be connected to-
gether locally to the controller and a single connection should
be made to the high current power ground (sense resistor
ground point).
OSCILLATOR, SHUTDOWN AND SYNC
A single external resistor, R_T, connected between the RT/
SYNC and GND pins sets the SM74203 oscillator frequency.
The SM74203 can also be synchronized to an external clock.
The external clock must have a higher frequency than the free
running oscillator frequency set by the R_T resistor. The clock
signal should be capacitively coupled into the RT/SYNC pin
with a 100 pF capacitor as shown in Figure 3. A peak voltage
level greater than 3.8V at the RT/SYNC pin is required for
detection of the sync pulse. The sync pulse width should be
set between 15 ns to 150 ns by the external components. The
R_T resistor is always required, whether the oscillator is free
running or externally synchronized. The voltage at the RT/
SYNC pin is internally regulated to 2V, and the typical delay
from a logic high at the RT/SYNC pin to the rise of the OUT
pin voltage is 120 ns. R_T should be located very close to the
device and connected directly to the pins of the controller (RT/
SYNC and GND).
FIGURE 3. Sync Operation
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PWM COMPARATOR AND SLOPE COMPENSATION
The PWM comparator compares the current ramp signal with
the error voltage derived from the error amplifier output. The
error amplifier output voltage at the COMP pin is offset by
1.4V and then further attenuated by a 3:1 resistor divider. The
PWM comparator polarity is such that 0V on the COMP pin
will result in a zero duty cycle at the controller output. For duty
cycles greater than 50%, current mode control circuits can
experience sub-harmonic oscillation. By adding an additional
fixed-slope voltage ramp signal (slope compensation) this os-
cillation can be avoided. Proper slope compensation damps
the double pole associated with current mode control (see the
Control Loop Compensation section) and eases the design of
the control loop compensator. The SM74203 generates the
slope compensation with a sawtooth-waveform current
source with a slope of 45 µA x f_SW, generated by the clock.
(See Figure 4) This current flows through an internal 2 kΩ
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