SM74203 Datasheet, PDF (16/24 Pages) Texas Instruments – SM74203 60V Low Side Controller for Boost and SEPIC

The sampling double pole quality factor is:
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FIGURE 7. Power Stage and Error Amp
One popular method for selecting the compensation compo-
nents is to create Bode plots of gain and phase for the power
stage and error amplifier. Combined, they make the overall
bandwidth and phase margin of the regulator easy to deter-
mine. Software tools such as Excel, MathCAD, and Matlab
are useful for observing how changes in compensation or the
power stage affect system gain and phase.
The power stage in a CCM peak current mode boost con-
verter consists of the DC gain, A_PS, a single low frequency
pole, f_LFP, the ESR zero, f_ZESR, a right-half plane zero, f_RHP,
and a double pole resulting from the sampling of the peak
current. The power stage transfer function (also called the
Control-to-Output transfer function) can be written:
The sampling double corner frequency is:
ω_n = π x f_SW
The natural inductor current slope is:
S_n = R_SNS x V_IN / L
The external ramp slope is:
S_e = 45 µA x (2000 + R_S1 + R_S2)] x f_SW
In the equation for A_PS, DC gain is highest when input voltage
and output current are at the maximum. In this the example
those conditions are V_IN = 16V and I_O = 500 mA.
DC gain is 44 dB. The low frequency pole f_P = 2πω_P is at
423Hz, the ESR zero f_Z = 2πω_Z is at 5.6 MHz, and the right-
half plane zero f_RHP = 2πω_RHP is at 61 kHz. The sampling
double-pole occurs at one-half of the switching frequency.
Proper selection of slope compensation (via R_S2) is most ev-
ident the sampling double pole. A well-selected R_S2 value
eliminates peaking in the gain and reduces the rate of change
of the phase lag. Gain and phase plots for the power stage
are shown in Figure 8.
Where the DC gain is defined as:
Where:
R_O = V_O / I_O
The system ESR zero is:
The low frequency pole is:
The right-half plane zero is:
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