DRV8332-HT Datasheet, PDF (19/26 Pages) Texas Instruments – THREE PHASE PWM MOTOR DRIVER

DRV8332-HT
www.ti.com
SLES274B – AUGUST 2013 – REVISED JANUARY 2014
APPLICATION INFORMATION
SYSTEM DESIGN RECOMMENDATIONS
Voltage of Decoupling Capacitor
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. The high frequency decoupling capacitor
should use ceramic capacitor with X5R or better rating. For a 50-V application, a minimum voltage rating of 63 V
is recommended.
Current Requirement of 12V Power Supply
The DRV8332 requires a 12V power supply for GVDD and VDD pins. The total supply current is pretty low at
room temp (less than 50mA), but the current could increase significantly when the device temperature goes too
high (e.g. above 125°C), especially at heave load conditions due to substrate current collection by 12V guard
rings. So it is recommended to design the 12V power supply with current capability at least 5-10% of your load
current and no less than 100mA to assure the device performance across all temperature range.
VREG Pin
The VREG pin is used for internal logic and should not be used as a voltage source for external circuitries. The
capacitor on VREG pin should be connected to AGND.
VDD Pin
The transient current in VDD pin could be significantly higher than average current through VDD pin. A low
resistive path to GVDD should be used. A 22-µF to 47-µF capacitor should be placed on VDD pin beside the
100-nF to 1-µF decoupling capacitor to provide a constant voltage during transient.
OTW Pin
OTW reporting indicates the device approaching high junction temperature. This signal can be used with MCU to
decrease system power when OTW is low in order to prevent OT shut down at a higher temperature.
No external pull up resistor or 3.3V power supply is needed for 3.3V logic. The OTW pin has an internal pullup
resistor connecting to an internal 3.3V to reduce external component count. For 5V logic, an external pull up
resistor to 5V is needed.
FAULT Pin
The FAULT pin reports any fault condition resulting in device shut down. No external pull up resistor or 3.3V
power supply is needed for 3.3V logic. The FAULT pin has an internal pullup resistor connecting to an internal
3.3V to reduce external component count. For 5V logic, an external pull upresistor to 5V is needed.
OC_ADJ Pin
For accurate control of the oevercurrent protection, the OC_ADJ pin has to be connected to AGND through an
OC adjust resistor.
PWM_X and RESET_X Pins
It is recommanded to connect these pins to either AGND or GND when they are not used, and these pins only
support 3.3V logic.
Mode Select Pins
Mode select pins (M1, M2, and M3) should be connected to either VREG (for logic high) or AGND for logic low. It
is not recommended to connect mode pins to board ground if 1-Ω resistor is used between AGND and GND.
Copyright © 2013–2014, Texas Instruments Incorporated
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