DRV8332-HT Datasheet, PDF (13/26 Pages) Texas Instruments – THREE PHASE PWM MOTOR DRIVER

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Figure 7 illustrates cycle-by-cycle operation with high
side OC event and Figure 8 shows cycle-by-cycle
operation with low side OC. Dashed lines are the
operation waveforms when no CBC event is triggered
and solide lines show the waveforms when CBC
event is triggered. In CBC current limiting mode,
when low side FET OC is detected, the device will
turn off the affected low side FET and keep the high
side FET at the same half bridge off until next PWM
cycle; when high side FET OC is detected, the device
will turn off the affected high side FET and turn on the
low side FET at the half bridge until next PWM cycle.
It is important to note that if the input to a half bridge
is held to a constant value when an over current
event occurs in CBC, then the associated half bridge
will be in a HI-Z state upon the over current event
ending. Cycling IN_X will allow OUT_X to resume
normal operation.
In OC latching shut down mode, the CBC current limit
and error recovery circuits are disabled and an
overcurrent condition will cause the device to
shutdown immediately. After shutdown, RESET_A,
RESET_B, and RESET_C must be asserted to
restore normal operation after the overcurrent
condition is removed.
For added flexibility, the OC threshold is
programmable using a single external resistor
connected between the OC_ADJ pin and AGND pin.
See Table 2 for information on the correlation
between programming-resistor value and the OC
threshold.
The values in Table 2 show typical OC thresholds for
a given resistor. Assuming a fixed resistance on the
OC_ADJ pin across multiple devices, a 20% device-
to-device variation in OC threshold measurements is
possible. Therefore, this system is designed for
system protection and not for precise current control.
Table 2. Programming-Resistor Values and OC
Threshold
OC-ADJUST RESISTOR
VALUES (kΩ)
30
36
39
43
47
56
68
MAXIMUM CURRENT BEFORE
OC OCCURS (A)
8.8
7.4
6.9
6.3
5.8
4.9
4.1
DRV8332-HT
SLES274B – AUGUST 2013 – REVISED JANUARY 2014
Table 2. Programming-Resistor Values and OC
Threshold (continued)
OC-ADJUST RESISTOR
VALUES (kΩ)
82
100
120
150
200
MAXIMUM CURRENT BEFORE
OC OCCURS (A)
3.4
2.8
2.4
1.9
1.4
It should be noted that a properly functioning
overcurrent detector assumes the presence of a
proper inductor or power ferrite bead at the power-
stage output. Short-circuit protection is not
guaranteed with direct short at the output pins of the
power stage.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the DRV8332 fully
protect the device in any power-up / down and
brownout situation. While powering up, the POR
circuit resets the overcurrent circuit and ensures that
all circuits are fully operational when the GVDD_X
and VDD supply voltages reach 9.8 V (typical).
Although GVDD_X and VDD are independently
monitored, a supply voltage drop below the UVP
threshold on any VDD or GVDD_X pin results in all
half-bridge outputs immediately being set in the high-
impedance (Hi-Z) state and FAULT being asserted
low. The device automatically resumes operation
when all supply voltage on the bootstrap capacitors
have increased above the UVP threshold.
DEVICE RESET
Three reset pins are provided for independent control
of half-bridges A, B, and C. When RESET_X is
asserted low, two power-stage FETs in half-bridges X
are forced into a high-impedance (Hi-Z) state.
A rising-edge transition on reset input allows the
device to resume operation after a shut-down fault.
That is, when half-bridge X has OC shutdown in CBC
mode, a low to high transition of RESET_X pin will
clear the fault and FAULT pin. When an OTSD
occurs or OC shutdown in Latching mode occurs, all
three RESET_A, RESET_B, and RESET_C need to
have a low to high transition to clear the fault and
reset FAULT signal.
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