DRV8332-HT Datasheet, PDF (12/26 Pages) Texas Instruments – THREE PHASE PWM MOTOR DRIVER

DRV8332-HT
SLES274B – AUGUST 2013 – REVISED JANUARY 2014
ERROR REPORTING
The FAULT and OTW pins are both active-low, open-
drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control
device.
Any fault resulting in device shutdown, such as
overtemperatue shut down, overcurrent shut-down, or
undervoltage protection, is signaled by the FAULT pin
going low. Likewise, OTW goes low when the device
junction temperature exceeds 125°C (see Table 1).
Table 1. Protection Mode Signal Descriptions
FAULT
0
0
1
1
OTW
0
1
0
1
DESCRIPTION
Overtemperature warning and
(overtemperature shut down or overcurrent
shut down or undervoltage protection) occurred
Overcurrent shut-down or GVDD undervoltage
protection occurred
Overtemperature warning
Device under normal operation
TI recommends monitoring the OTW signal using the
system microcontroller and responding to an OTW
signal by reducing the load current to prevent further
heating of the device resulting in device
overtemperature shutdown (OTSD).
To reduce external component count, an internal
pullup resistor to internal VREG (3.3 V) is provided on
both FAULT and OTW outputs. Level compliance for
5-V logic can be obtained by adding external pull-up
resistors to 5 V (see the Electrical Characteristics
section of this data sheet for further specifications).
DEVICE PROTECTION SYSTEM
The DRV8332 contains advanced protection circuitry
carefully designed to facilitate system integration and
ease of use, as well as to safeguard the device from
permanent failure due to a wide range of fault
conditions such as short circuits, overcurrent,
overtemperature, and undervoltage. The DRV8332
responds to a fault by immediately setting the half
bridge outputs in a high-impedance (Hi-Z) state and
asserting the FAULT pin low. In situations other than
overcurrent or overtemperature, the device
automatically recovers when the fault condition has
been removed or the gate supply voltage has
increased. For highest possible reliability, reset the
device externally no sooner than 1 second after the
shutdown when recovering from an overcurrent shut
down (OCSD) or OTSD fault.
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Bootstrap Capacitor Under Voltage Protection
When the device runs at a low switching frequency
(e.g. less than 10 kHz with a 100-nF bootstrap
capacitor), the bootstrap capacitor voltage might not
be able to maintain a proper voltage level for the
high-side gate driver. A bootstrap capacitor
undervoltage protection circuit (BST_UVP) will
prevent potential failure of the high-side MOSFET.
When the voltage on the bootstrap capacitors is less
than the required value for safe operation, the
DRV8332 will initiate bootstrap capacitor recharge
sequences (turn off high side FET for a short period)
until the bootstrap capacitors are properly charged for
safe operation. This function may also be activated
when PWM duty cycle is too high (e.g. less than 20
ns off time at 10 kHz). Note that bootstrap capacitor
might not be able to be charged if no load or
extremely light load is presented at output during
BST_UVP operation, so it is recommended to turn on
the low side FET for at least 50 ns for each PWM
cycle to avoid BST_UVP operation if possible.
For all applications, it is recommended to add 26-Ω
resistor between the GVDD power supply and
GVDD_X pins to limit the inrush current on the
internal bootstrap diodes.
Overcurrent (OC) Protection
The DRV8332 has independent, fast-reacting current
detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
FETs. There are two settings for OC protection
through mode selection pins: cycle-by-cycle (CBC)
current limiting mode and OC latching (OCL) shut
down mode.
In CBC current limiting mode, the detector outputs
are monitored by two protection systems. The first
protection system controls the power stage in order to
prevent the output current from further increasing,
i.e., it performs a CBC current-limiting function rather
than prematurely shutting down the device. This
feature could effectively limit the inrush current during
motor start-up or transient without damaging the
device. During short to power and short to ground
conditions, the current limit circuitry might not be able
to control the current to a proper level, a second
protection system triggers a latching shutdown,
resulting in the related half bridge being set in the
high-impedance (Hi-Z) state. Current limiting and
overcurrent protection are independent for half-
bridges A, B, and C, respectively.
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