DRV8332-HT Datasheet, PDF (14/26 Pages) Texas Instruments – THREE PHASE PWM MOTOR DRIVER

DRV8332-HT
SLES274B – AUGUST 2013 – REVISED JANUARY 2014
DIFFERENT OPERATIONAL MODES
The DRV8332 supports two different modes of
operation:
1. Three-phase (3PH) or three half bridges (HB)
with CBC current limit
2. Three-phase or three half bridges with OC
latching shutdown (no CBC current limit)
Because each half bridge has independent supply
and ground pins, a shunt sensing resistor can be
inserted between PVDD to PVDD_X or GND_X to
GND (ground plane). A high side shunt resistor
between PVDD and PVDD_X is recommended for
differential current sensing because a high bias
voltage on the low side sensing could affect device
operation. If low side sensing has to be used, a shunt
resistor value of 10 mΩ or less or sense voltage 100
mV or less is recommended.
and Figure 9 show the three-phase application
examples, and Figure 10 shows how to connect to
DRV8332 with some simple logic to accommodate
conventional 6 PWM inputs control.
We recommend using complementary control
scheme for switching phases to prevent circulated
energy flowing inside the phases and to make current
limiting feature active all the time. Complementary
control scheme also forces the current flowing
through sense resistors all the time to have a better
current sensing and control of the system.
www.ti.com
Figure 11 shows six steps trapezoidal scheme with
hall sensor control and Figure 12 shows six steps
trapezoidal scheme with sensorless control. The hall
sensor sequence in real application might be different
than the one we showed in Figure 11 depending on
the motor used. Please check motor manufacture
datasheet for the right sequence in applications. In
six step trapezoidal complementary control scheme, a
half bridge with larger than 50% duty cycle will have a
positive current and a half bridge with less than 50%
duty cycle will have a negative current. For normal
operation, changing PWM duty cycle from 50% to
100% will adjust the current from 0 to maximum value
with six steps control. It is recommanded to apply a
minimum 50 ns to 100 ns PWM pulse at each
switching cycle at lower side to properly charge the
bootstrap cap. The impact of minimum pulse at low
side FET is pretty small, e.g., the maximum duty
cycle is 99.9% with 100ns minimum pulse on low
side. RESET_Xpin can be used to get channel X into
high impedance mode. If you prefer PWM switching
one channel but hold low side FET of the other
channel on (and third channel in Hi-Z) for 2-quadrant
mode, OT latching shutdown mode is recommended
to prevent the channel with low side FET on stuck in
Hi-Z during OC event in CBC mode.
The DRV8332 can also be used for sinusoidal
waveform control and field oriented control. Please
check TI website MCU motor control library for
control algorithms.
During T_OC Period
PVDD
PWM_HS
Load
Current
CBC with High Side OC
Current Limit
PWM_LS
GND_X
Load
PWM_HS
PWM_LS
T_HS T_OC T_LS
Figure 7. Cycle-by-Cycle Operation with High Side OC
(dashed line: normal operation; solid line: CBC event)
14
Submit Documentation Feedback
Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: DRV8332-HT