TCA9555_16 Datasheet, PDF (17/46 Pages) Texas Instruments – Low-Voltage 16-Bit I2C and SMBus I/O Expander with Interrupt Output and Configuration Registers

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Programming (continued)
TCA9555
SCPS200D – JULY 2009 – REVISED JULY 2016
Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Configuration
Register
DQ
FF
CLK Q
Read Pulse
Data From
Shift Register
Write Polarity
Pulse
DQ
FF
CLK Q
Output Port
Register
Output Port
Register Data
V_CC
Q1
100 kΩ
Input Port
Register
DQ
FF
CLK Q
I/O Pin
Q2
GND
Input Port
Register Data
To INT
DQ
FF
CLK Q
Polarity Inversion
Register
Polarity
Register Data
Figure 23. Simplified Schematic of P-Port I/Os
9.5.2 I²C Interface
The TCA9555 has a standard bidirectional I²C interface that is controlled by a master device in order to be
configured or read the status of this device. Each slave on the I²C bus has a specific device address to
differentiate between other slave devices that are on the same I²C bus. Many slave devices require configuration
upon startup to set the behavior of the device. This is typically done when the master accesses internal register
maps of the slave, which have unique register addresses. A device can have one or multiple registers where
data is stored, written, or read. For more information see the Understanding the I2C Bus application report,
SLVA704.
The physical I²C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to V_CC through a pull-up resistor. The size of the pull-up resistor is determined by the amount
of capacitance on the I²C lines. For further details, refer to I²C Pull-up Resistor Calculation application report,
SLVA689. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL
lines are high after a STOP condition.
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