AM1808_14 Datasheet, PDF (150/265 Pages) Texas Instruments – Microprocessor

AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
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CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
1
2
3
3
4
4
5
6
7
2
3
3
Bit(n1)
8
(n2)
9
11
10
FSX (XDATDLY=00b)
12
DX
Bit 0
14
13 (A)
Bit(n1)
13 (A)
(n2)
A. No. 13 applies to the first data bit only when XDATDLY ≠ 0.
Figure 6-32. McBSP Timing
(n3)
(n3)
Table 6-65. Timing Requirements for McBSP0 FSR When GSYNC = 1 (see Figure 6-33)
NO.
1 t_su(FRH-CKSH)
2 t_h(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
1.3V, 1.2V
MIN MAX
4
4
1.1V
MIN MAX
4.5
4
1.0V
MIN MAX
5
4
UNIT
ns
ns
Table 6-66. Timing Requirements for McBSP1 FSR When GSYNC = 1 (see Figure 6-33)
NO.
1 t_su(FRH-CKSH)
2 t_h(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
1.3V, 1.2V
MIN MAX
5
4
1.1V
MIN MAX
5
4
1.0V
MIN MAX
10
4
UNIT
ns
ns
CLKS
FSR external
1
2
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 6-33. FSR Timing When GSYNC = 1
150 Peripheral Information and Electrical Specifications
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