AM1808_14 Datasheet, PDF (103/265 Pages) Texas Instruments – Microprocessor

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AM1808
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-21. Timing Requirements for EMIFA Asynchronous Memory Interface ⁽¹⁾
1.2V
1.1V
1.0V
NO.
UNIT
MIN MAX MIN MAX MIN MAX
READS and WRITES
E t_c(CLK)
Cycle time, EMIFA module clock
6.75
13.33
20
ns
2 t_{w(EM_WAIT)}
Pulse duration, EM_WAIT assertion and deassertion
2E
2E
2E
ns
READS
12 t_{su(EMDV-EMOEH)} Setup time, EM_D[15:0] valid before EM_OE high
3
5
7
ns
13 t_{h(EMOEH-EMDIV)} Hold time, EM_D[15:0] valid after EM_OE high
0
0
0
ns
14 ^{tsu (EMOEL-}
EMWAIT)
Setup Time, EM_WAIT asserted before end of Strobe
Phase
4E+3
4E+3
4E+3
ns
WRITES
28 ^{tsu (EMWEL-}
EMWAIT)
Setup Time, EM_WAIT asserted before end of Strobe
Phase
4E+3
4E+3
4E+3
ns
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns
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