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| AM1808_14 Datasheet, PDF (104/265 Pages) Texas Instruments – Microprocessor | |||
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AM1808
SPRS653E â FEBRUARY 2010 â REVISED MARCH 2014
www.ti.com
NO.
1
td(TURNAROUND)
3
tc(EMRCYCLE)
4
tsu(EMCEL-EMOEL)
5
th(EMOEH-EMCEH)
6
tsu(EMBAV-EMOEL)
7
th(EMOEH-EMBAIV)
8
tsu(EMBAV-EMOEL)
9
th(EMOEH-EMAIV)
10 tw(EMOEL)
11
td(EMWAITH-EMOEH)
28
tsu(EMARW-EMOEL)
29
th(EMOEH-EMARW)
15
tc(EMWCYCLE)
16
tsu(EMCEL-EMWEL)
17
th(EMWEH-EMCEH)
18
tsu(EMDQMV-EMWEL)
19
th(EMWEH-EMDQMIV)
20
tsu(EMBAV-EMWEL)
21
th(EMWEH-EMBAIV)
Table 6-22. Switching Characteristics for EMIFA Asynchronous Memory Interface (1) (2) (3)
PARAMETER
MIN
READS and WRITES
Turn around time
(TA)*E - 3
READS
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E - 3
EMIF read cycle time (EW = 1)
(RS+RST+RH+EWC)*E - 3
Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 0)
(RS)*E-3
Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 1)
-3
Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 0)
(RH)*E - 3
Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 1)
-3
Output setup time, EMA_BA[1:0] valid to EMA_OE low
(RS)*E-3
Output hold time, EMA_OE high to EMA_BA[1:0] invalid
(RH)*E-3
Output setup time, EMA_A[13:0] valid to EMA_OE low
(RS)*E-3
Output hold time, EMA_OE high to EMA_A[13:0] invalid
(RH)*E-3
EMA_OE active low width (EW = 0)
(RST)*E-3
EMA_OE active low width (EW = 1)
(RST+EWC)*E-3
Delay time from EMA_WAIT deasserted to EMA_OE high
3E-3
Output setup time, EMA_A_RW valid to EMA_OE low
(RS)*E-3
Output hold time, EMA_OE high to EMA_A_RW invalid
(RH)*E-3
WRITES
EMIF write cycle time (EW = 0)
(WS+WST+WH)*E-3
EMIF write cycle time (EW = 1)
(WS+WST+WH+EWC)*E - 3
Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 0)
Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 1)
Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 0)
Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 1)
Output setup time, EMA_BA[1:0] valid to EMA_WE low
Output hold time, EMA_WE high to EMA_BA[1:0] invalid
Output setup time, EMA_BA[1:0] valid to EMA_WE low
Output hold time, EMA_WE high to EMA_BA[1:0] invalid
(WS)*E - 3
-3
(WH)*E-3
-3
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WH)*E-3
1.3V, 1.2V, 1.1V, 1.0V
Nom
MAX
(TA)*E
(TA)*E + 3
(RS+RST+RH)*E
(RS+RST+RH+EWC)*E
(RS)*E
0
(RH)*E
0
(RS)*E
(RH)*E
(RS)*E
(RH)*E
(RST)*E
(RST+EWC)*E
4E
(RS)*E
(RH)*E
(RS+RST+RH)*E + 3
(RS+RST+RH+EWC)*E + 3
(RS)*E+3
+3
(RH)*E + 3
+3
(RS)*E+3
(RH)*E+3
(RS)*E+3
(RH)*E+3
(RST)*E+3
(RST+EWC)*E+3
4E+3
(RS)*E+3
(RH)*E+3
(WS+WST+WH)*E
(WS+WST+WH+EWC)*E
(WS)*E
0
(WH)*E
0
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS+WST+WH)*E+3
(WS+WST+WH+EWC)*E +
3
(WS)*E + 3
+3
(WH)*E+3
+3
(WS)*E+3
(WH)*E+3
(WS)*E+3
(WH)*E+3
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These
parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-
1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256].
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz,
E=10ns.
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified
by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
104 Peripheral Information and Electrical Specifications
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