TIBPSG507AC Datasheet, PDF (14/19 Pages) Texas Instruments – 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR

TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
APPLICATION INFORMATION
The TIBPSG507AC is used in this application to generate the required memory timing control signals (RAS, CAS,
etc.) for the memory timing controller.
RFC
Refresh
Timer
REFREQ
Clock
Generator
AS
Microprocessor
REFEQ
Memory
Timing
Controller
TIBPSG507A
OSC
CLK
RFC
RESET
WAIT
R/W
A22
ALE
SN74ALS6301
Dynamic
Memory
Controller
SN74ALS6301
VCC
LE
Q0-Q8
RAASI
CAASI
MSEL
MC1
OE
CS
Address
2
Memory Bank Signals
SEL0,1
Dynamic RAM
A0-A8
Bank0
1 Meg x 32 Bit
TMS4C1027
RAS0
CAS0
W
A0-A8
RAS1
CAS1
W
Bank1
1 Meg x 32 Bit
TMS4C1027
A0-A8
RAS2
CAS2
W
Bank2
1 Meg x 32 Bit
TMS4C1027
A0-A8
RAS3
CAS3
W
Bank3
1 Meg x 32 Bit
TMS4C1027
Data
For detailed information, please see the Systems Solution for Static Column Decode Application Report.
Figure 5
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