TIBPSG507AC Datasheet, PDF (10/19 Pages) Texas Instruments – 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR

TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
glossary — timing model
tpd₍₁₎ — Maximum time interval from the time a signal edge is received at any input pin to the time any logically
affected combinational output pin delivers a response.
t_pd(2) — Maximum time interval from a positive edge on the clock input pin to data delivery on the output pin
corresponding to any output SR register.
t_pd(3) — Maximum time interval from the positive edge on the clock input pin to the response on any logically
affected combinational configured output (at the pin), where data origin is any internal SR register
or counter bit.
t_su(1) — Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin when data affects the S or R line of any output SR register.
t_su(2) — Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin when data affects the S or R line of any internal SR register.
t_su(3) — Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin only when entering data on the CNT/HLD0 line.
t_su(4) — Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin only when entering data on the SCLR0 line.
t_min(1) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using
feedback from any internal SR register or counter bit to feed the S or R line of any output SR register.
t_min(2) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using
feedback from any internal SR register to feed the S or R line of any internal SR register.
t_min(3) — Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using
feedback from any internal SR register or counter bit to feed SCLR0 or CNT/HLD0.
tpd(1) = 20 ns
tpd(2) = 10 ns
tpd(3) = 25 ns
PARAMETER VALUES FOR TIMING MODEL
tsu(1) = 12 ns†
tsu(2) = 12 ns†
tsu(3) = 25 ns
tsu(4) = 20 ns
tmin(1) = 17 ns
tmin(2) = 17 ns
tmin(3) = 25 ns
INTERNAL NODE NUMBERS
SCLR0
25
CNTHLD0 28
SCLR1
SET 26
CNTHLD1 SET 29
RESET 27
RESET 30
C0-C5
55-60
† _{Use tsu = 19 ns for applications where the setup time for S/R↓ inputs are required.}
P0-P7
Q0-Q7
SET 31-38
RESET 39-46
RESET 47-54
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