TIBPSG507AC Datasheet, PDF (13/19 Pages) Texas Instruments – 13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR

TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
f_max with external feedback
The configuration shown is a typical state-machine design with feedback signals sent off-chip. This external
feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest
path defining the clock period is the sum of the clock-to-output delay time and the setup time for the input or
feedback signals (t_su + t_pd CLK to Q).
) ^{Thus: fmax with external feedback =} tsu
1
tpd CLK to Q
CLK
Input
Logic
Array
Internal
SR
Registers
Output
SR
Registers
Next Device
tsu
tpd
CLK to Q
Figure 4
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