MSP430F5172_16 Datasheet, PDF (14/117 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430F5172, MSP430F5152, MSP430F5132
MSP430F5171, MSP430F5151, MSP430F5131
SLAS619P – AUGUST 2010 – REVISED MAY 2016
www.ti.com
5 Specifications
5.1 Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
Voltage V_CC applied at DVCC to DVSS
Voltage V_IO applied at VIO to DVSS
Voltage applied to any pin (excluding VCORE)⁽²⁾
Diode current at any device pin
–0.3
4.1 V
V
–0.3
6.1 V
V
–0.3 V_CC + 0.3
V
±2
mA
Maximum operating junction temperature, T_J
Storage temperature, T_stg
95
°C
–55
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V_SS. V_CORE is for internal device usage only. No external DC loading or voltage should be applied.
5.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
V_(ESD) Electrostatic discharge _{Charged-device model (CDM), per JEDEC specification JESD22-C101(2)}
VALUE
±1000
±250
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
Typical values are specified at V_CC = 3.3 V and T_A = 25°C (unless otherwise noted)
V_CC
V_IO
V_SS
T_A
T_J
C_(VCORE)
C_(DVCC)/
C_(VCORE)
PMMCOREVx = 0
Supply voltage during program execution and flash
programming
V(AVCC) = V(DVCC) = V_CC(1)(2)
PMMCOREVx = 0, 1
PMMCOREVx = 0, 1, 2
PMMCOREVx = 0, 1, 2, 3
Supply voltage of pins P1.6, P1.7, P2.0 to P2.7, P3.0, and P3.1 supplied by VIO⁽³⁾
Supply voltage V(AVSS) = V(DVSS) = V_SS
Operating free-air temperature
Operating junction temperature
Recommended capacitor at VCORE⁽⁴⁾
Capacitor ratio of DVCC to VCORE
MIN NOM MAX UNIT
1.8
3.6
2.0
3.6
V
2.2
3.6
2.4
3.6
1.8
5.5 V
0
V
–40
85 °C
–40
85 °C
470
nF
10
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between V(AVCC) and V(DVCC) can
be tolerated during power up and operation.
(2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.28 threshold parameters for
the exact values and further details.
(3) TI recommends powering DVCC and AVCC before powering DVIO. At DVCC and AVCC voltages higher than 1.8 V, the maximum
difference of 0.3 V between DVIO and DVCC and AVCC can be exceeded.
(4) A capacitor tolerance of ±20% or better is required.
14
Specifications
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