TMS320DM641_08 Datasheet, PDF (97/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

Reset
For information on peripheral selection at the rising edge of RESET, see the Device Configuration section of
this data manual.
4.6.1
Reset Electrical Data/Timing
Table 4−10. Timing Requirements for Reset (see Figure 4−11)
−400
−500
NO.
−600
UNIT
MIN
MAX
1
t_w(RST)
Width of the RESET pulse
250
µs
16 t_su(boot)
Setup time, boot configuration bits valid before RESET high^†
4E or 4C^‡
ns
17 t_h(boot)
Hold time, boot configuration bits valid after RESET high^†
4P^§
ns
† _{AEA[22:19], LENDIAN, and HD5 are the boot configuration pins during device reset.}
‡ _{E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns.}
Select the MIN parameter value, whichever value is larger.
§ _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
Table 4−11. Switching Characteristics Over Recommended Operating Conditions During Reset^§¶#
(see Figure 4−11)
NO.
PARAMETER
−400
−500
−600
UNIT
MIN
MAX
2
t_d(RSTL-ECKI)
Delay time, RESET low to AECLKIN synchronized internally
2E 3P + 20E ns
3
t_d(RSTH-ECKI)
Delay time, RESET high to AECLKIN synchronized internally
2E 8P + 20E ns
4
t_{d(RSTL-ECKO1HZ)}
Delay time, RESET low to AECLKOUT1 high impedance
2E
ns
5
t_{d(RSTH-ECKO1V)}
Delay time, RESET high to AECLKOUT1 valid
8P + 20E ns
6
t_{d(RSTL-EMIFZHZ)}
Delay time, RESET low to EMIF Z high impedance
2E 3P + 4E ns
7
t_{d(RSTH-EMIFZV)}
Delay time, RESET high to EMIF Z valid
16E 8P + 20E ns
8
t_{d(RSTL-EMIFHIV)}
Delay time, RESET low to EMIF high group invalid
2E
ns
9
t_{d(RSTH-EMIFHV)}
Delay time, RESET high to EMIF high group valid
8P + 20E ns
10 t_{d(RSTL-EMIFLIV)}
Delay time, RESET low to EMIF low group invalid
2E
ns
11 t_{d(RSTH-EMIFLV)}
Delay time, RESET high to EMIF low group valid
8P + 20E ns
12 t_{d(RSTL-LOWIV)}
Delay time, RESET low to low group invalid
0
ns
13 t_d(RSTH-LOWV)
Delay time, RESET high to low group valid
11P ns
14 t_d(RSTL-ZHZ)
Delay time, RESET low to Z group high impedance
0
ns
15 t_d(RSTH-ZV)
Delay time, RESET high to Z group valid
2P
8P ns
§ _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
¶ _{E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.}
# _{EMIF Z group consists of: AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,}
AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT.
EMIF high group consists of: AHOLDA (when the corresponding AHOLD input is high)
EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding AHOLD input is low)
Low group consists of:
Z group consists of:
HD[15:0], VP0D[0]/CLKX0, VP0D[1]/FSX0, VP0D[2]/DX0, CLKR0, VP0D[5]/FSR0, TOUT0, TOUT1, VDAC,
GP0[7:0], HR/W, HDS2, HDS1, HCS, HCNTL1, HAS, HCNTL0, HHWIL (16-bit HPI mode only), HRDY, HINT, and
VP0D[4,3].
VP1 signals apply to DM641 only:
VP1D[0]/CLKX1, VP1D[1]/FSX1, VP1D[2]/DX1, VP1D[6]/CLKR1, VP1D[5]/FSR1, and VP1D[4,3].
June 2003 − Revised October 2005
SPRS222E
97