TMS320DM641_08 Datasheet, PDF (150/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

Video Port
4.13.3.2 Video Data and Control Timing (Video Capture Mode)
Table 4−56. Timing Requirements in Video Capture Mode for Video Data and Control Inputs
(see Figure 4−51)
NO.
1 t_{su(VDATV-VKIH)} Setup time, VPxDx valid before VPxCLKINx high
2 t_{h(VDATV-VKIH)} Hold time, VPxDx valid after VPxCLKINx high
3 t_{su(VCTLV-VKIH)} Setup time, VPxCTLx valid before VPxCLKINx high
4 t_{h(VCTLV-VKIH)} Hold time, VPxCTLx valid after VPxCLKINx high
−400
−500
−600
MIN MAX
2.9
0.5
2.9
0.5
UNIT
ns
ns
ns
ns
VPxCLKINx
1
2
VPxD[7:0] (Input)
3
4
VPxCTLx (Input)
Figure 4−51. Video Port Capture Data and Control Input Timing
150 SPRS222E
June 2003 − Revised October 2005