TMS320DM641_08 Datasheet, PDF (140/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

Multichannel Buffered Serial Port (McBSP)
Table 4−44. Switching Characteristics Over Recommended Operating Conditions for McBSP^†‡
(see Figure 4−44)
NO.
PARAMETER
−400
−500
−600
UNIT
MIN
MAX
1
t_{d(CKSH-CKRXH)}
2
t_c(CKRX)
3
t_w(CKRX)
4
t_d(CKRH-FRV)
9
t_d(CKXH-FXV)
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated
from CLKS input
Cycle time, CLKR/X
CLKR/X int
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
Delay time, CLKR high to internal FSR valid
CLKR int
Delay time, CLKX high to internal FSX valid
CLKX int
CLKX ext
1.4
4P or 6.67^§¶#
C − 1^||
−2.1
−1.7
1.7
10 ns
ns
C + 1^|| ns
3 ns
3
ns
9
12 t_{dis(CKXH-DXHZ)}
13 t_d(CKXH-DXV)
Disable time, DX high impedance following last data bit
from CLKX high
Delay time, CLKX high to DX valid
CLKX int
CLKX ext
CLKX int
CLKX ext
−3.9
−2.1
−3.9 + D1k
−2.1 + D1k
4
ns
9
4 + D2k
9 + D2k ^ns
Delay time, FSX high to DX valid
FSX int
−2.3 + D1^h 5.6 + D2^h
14 t_d(FXH-DXV)
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
1.9 + D1^h
ns
9 + D2^h
† _{CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.}
‡ _{Minimum delay times also represent minimum output hold times.}
§ _{Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based}
on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
¶ _{P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.}
# _{Use whichever value is greater.}
|| _{C = H or L}
S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
kExtra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
hExtra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
140 SPRS222E
June 2003 − Revised October 2005