TMS320DM641_08 Datasheet, PDF (131/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

Inter-Integrated Circuit (I2C)
4.10.3 I2C Electrical Data/Timing
4.10.3.1 Inter-Integrated Circuits (I2C) Timing
Table 4−36. Timing Requirements for I2C Timings^† (see Figure 4−38)
−400
−500
−600
NO.
STANDARD
FAST
UNIT
MODE
MODE
1
t_c(SCL)
Cycle time, SCL
2
t_{su(SCLH-SDAL)}
Setup time, SCL high before SDA low (for a repeated START
condition)
MIN MAX
10
4.7
MIN MAX
2.5
µs
0.6
µs
3
t_h(SCLL-SDAL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
0.6
µs
4
t_w(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
5
t_w(SCLH)
Pulse duration, SCL high
4
0.6
µs
6
t_{su(SDAV-SDLH)} Setup time, SDA valid before SCL high
250
100^‡
ns
7
t_h(SDA-SDLL) Hold time, SDA valid after SCL low (For I²C bus™ devices)
0^§
0^§ 0.9^¶ µs
8
t_w(SDAH)
Pulse duration, SDA high between STOP and START conditions 4.7
1.3
µs
9
t_r(SDA)
Rise time, SDA
1000 20 + 0.1C_b# 300 ns
10
t_r(SCL)
Rise time, SCL
1000 20 + 0.1C_b# 300 ns
11
t_f(SDA)
Fall time, SDA
300 20 + 0.1C_b# 300 ns
12
t_f(SCL)
Fall time, SCL
300 20 + 0.1C_b# 300 ns
13 t_{su(SCLH-SDAH)} Setup time, SCL high before SDA high (for STOP condition)
4
0.6
µs
14
t_w(SP)
Pulse duration, spike (must be suppressed)
0 50 ns
15
C_b#
Capacitive load for each bus line
400
400 pF
† _{The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.}
‡ _{A Fast-mode I}2_{C-bus™ device can be used in a Standard-mode I}2_{C-bus™ system, but the requirement tsu(SDA−SCLH) ≥ 250 ns must then be met.}
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t_r max + t_{su(SDA−SCLH)} = 1000 + 250 = 1250 ns (according to the Standard-mode
I²C-Bus Specification) before the SCL line is released.
§ _{A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined}
region of the falling edge of SCL.
¶ _{The maximum th(SDA−SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.}
# _{Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.}
11
9
SDA
8
4
10
6
5
14
13
SCL
1
12
3
7
2
3
Stop Start
Repeated
Start
Figure 4−38. I2C Receive Timings
Stop
June 2003 − Revised October 2005
SPRS222E 131