TMS320DM641_08 Datasheet, PDF (119/179 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processors

External Memory Interface (EMIIF)
4.8.3.4 HOLD/HOLDA Timing
Table 4−28. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module^† (see Figure 4−32)
NO.
3 t_{h(HOLDAL-HOLDL)} Hold time, HOLD low after HOLDA low
† _{E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.}
−400
−500
−600
MIN MAX
E
UNIT
ns
Table 4−29. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module^{†‡§} (see Figure 4−32)
NO.
PARAMETER
−400
−500
−600
UNIT
MIN MAX
1
t_{d(HOLDL-EMHZ)}
2
t_{d(EMHZ-HOLDAL)}
4
t_{d(HOLDH-EMLZ)}
5
t_{d(EMLZ-HOLDAH)}
6
t_{d(HOLDL-EKOHZ)}
7
t_{d(HOLDH-EKOLZ)}
Delay time, HOLD low to EMIFA Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIFA Bus low impedance to HOLDA high
Delay time, HOLD low to AECLKOUTx high impedance
Delay time, HOLD high to AECLKOUTx low impedance
2E
¶ _ns
0 2E ns
2E 7E ns
0 2E ns
2E
¶ _ns
2E 7E ns
† _{E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.}
‡ _{EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and}
AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
§ _{The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,}
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 4−32.
¶ _{All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay}
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus^†
DSP Owns Bus
2
1
DM641/DM640
External Requestor
Owns Bus
3
DSP Owns Bus
5
4
DM641/DM640
AECLKOUTx^‡
(EKxHZ = 0)
6
7
AECLKOUTx^‡
(EKxHZ = 1)
† _{EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and}
AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.
‡ _{The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,}
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 4−32.
Figure 4−32. HOLD/HOLDA Timing for EMIFA
June 2003 − Revised October 2005
SPRS222E 119