DAC38J82_15 Datasheet, PDF (97/119 Pages) Texas Instruments – DAC3xJ82 Dual-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface

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DAC37J82, DAC38J82
SLASE16B – JANUARY 2014 – REVISED MAY 2014
Register
Name
config106
WRITE TO
CLEAR
Addr
(Hex)
0x6A
Table 137. Register Name: config106 – Address: 0x6A, Default: 0x0000
Bit Name
15:8 alarm_lane_
error(6)
7:4 reserved
3:0 alarm_fifo_
flags(0)
Function
Lane0 errors:
bit15 = multiframe alignment error
bit14 = frame alignment error
bit13 = link configuration error
bit12 = elastic buffer overflow (bad RBD value)
bit11 = elastic buffer match error. The first non-/K/ doesn’t match
“match_ctrl” and “match_data” programmed values.
bit10 = code synchronization error
bit9 = 8b/10b not-in-table code error
bit8 = 8b/10b disparity error
Reserved
Lane0 FIFO errors:
bit3 = write_error : Asserted if write request and FIFO is full
bit2 = write_full : FIFO is FULL
bit1 = read_error : Asserted if read request with empty FIFO
bit0 = read_empty : FIFO is empty
Register
Name
config107
WRITE
TO
CLEAR
Addr
(Hex)
0x6B
Table 138. Register Name: config107 – Address: 0x6B, Default: 0x0000
Bit Name
15:8 alarm_lane_
error(7)
7:4 reserved
3:0 alarm_fifo_
flags(0)
Function
Lane7 errors:
bit15 = multiframe alignment error
bit14 = frame alignment error
bit13 = link configuration error
bit12 = elastic buffer overflow (bad RBD value)
bit11 = elastic buffer match error. The first non-/K/ doesn’t match
“match_ctrl” and “match_data” programmed values.
bit10 = code synchronization error
bit9 = 8b/10b not-in-table code error
bit8 = 8b/10b disparity error
Reserved
Lane0 FIFO errors:
bit3 = write_error : Asserted if write request and FIFO is full
bit2 = write_full : FIFO is FULL
bit1 = read_error : Asserted if read request with empty FIFO
bit0 = read_empty : FIFO is empty
Default
Value
0x00
0000
0000
Default
Value
0x00
0000
0000
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DAC37J82 DAC38J82
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