DAC38J82_15 Datasheet, PDF (54/119 Pages) Texas Instruments – DAC3xJ82 Dual-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface

DAC37J82, DAC38J82
SLASE16B – JANUARY 2014 – REVISED MAY 2014
www.ti.com
7.3.27 Reference Operation
The DAC37J82/DAC38J82 uses a bandgap reference and control amplifier for biasing the full-scale output
current. The full-scale output current is set by applying an external resistor R_BIAS to pin BIASJ. The bias current
I_BIAS through resistor R_BIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default
full-scale output current equals 64 times this bias current and can thus be expressed as:
IOUT_FS = 16 x I_BIAS = 64 x V_EXTIO / R_BIAS
The DAC37J82/DAC38J82 has a 4-bit coarse gain control coarse_dac(3:0) in the configtbd register. Using gain
control, the IOUT_FS can be expressed as:
IOUT_FS = (coarse_dac + 1) /16 x I_BIAS x 64 = (coarse_dac + 1) /16 x V_EXTIO / R_BIAS x 64
where V_EXTIO is the voltage at pin EXTIO. The bandgap reference voltage delivers an accurate voltage of 0.9V.
This reference is active when extref_ena = ‘0’ in configtbd. An external decoupling capacitor C_EXT of 0.1 µF
should be connected externally to pin EXTIO for compensation. The bandgap reference can additionally be used
for external reference operation. In that case, an external buffer with high impedance input should be applied in
order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be disabled and
overridden by an external reference by setting the extref_ena control bit. Capacitor C_EXT may hence be omitted.
Pin EXTIO thus serves as either input or output node.
The full-scale output current can be adjusted from 30 mA down to 10 mA by varying resistor R_BIAS or changing
the externally applied reference voltage.
7.3.28 Analog Outputs
The CMOS DACs consist of a segmented array of PMOS current sources, capable of sourcing a full-scale output
current up to 30 mA. Differential current switches direct the current to either one of the complimentary output
nodes IOUTP or IOUTN. Complimentary output currents enable differential operation, thus canceling out
common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion
components, and increasing signal output power by a factor of four.
The full-scale output current is set using external resistor R_BIAS in combination with an on-chip bandgap voltage
reference source (+0.9 V) and control amplifier. Current I_BIAS through resistor R_BIAS is mirrored internally to
provide a maximum full-scale output current equal to 16 times I_BIAS.
The relation between IOUTP and IOUTN can be expressed as:
IOUT_FS = IOUTP + IOUTN
We will denote current flowing into a node as –current and current flowing out of a node as +current. Since the
output stage is a current source the current flows from the IOUTP and IOUTN pins. The output current flow in
each pin driving a resistive load can be expressed as:
IOUTP = IOUT_FS x CODE / 65536
IOUTN = IOUT_FS x (65535 – CODE) / 65536
where CODE is the decimal representation of the DAC data input word.
For the case where IOUTP and IOUTN drive resistor loads R_L directly, this translates into single ended voltages
at IOUTP and IOUTN:
VOUTP = IOUT1 x R_L
VOUTN = IOUT2 x R_L
Assuming that the data is full scale (65535 in offset binary notation) and the R_L is 25 Ω, the differential voltage
between pins IOUTP and IOUTN can be expressed as:
VOUTP = 20mA x 25 Ω = 0.5 V
VOUTN = 0mA x 25 Ω = 0 V
VDIFF = VOUTP – VOUTN = 0.5V
Note that care should be taken not to exceed the compliance voltages at node IOUTP and IOUTN, which would
lead to increased signal distortion.
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