DAC38J82_15 Datasheet, PDF (58/119 Pages) Texas Instruments – DAC3xJ82 Dual-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface

DAC37J82, DAC38J82
SLASE16B – JANUARY 2014 – REVISED MAY 2014
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The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency.
DACCLK FREQUENCY
(MHz)
1474.56
1474.56
1474.56
1474.56
Table 29. PFD and CP Operation
M DIVIDER
12
24
48
64
PFD UPDATE RATE (MHz)
122.88
61.44
30.72
15.36
pll_m(7:0)
00001011
00010111
00101111
00111111
The N divider in the loop allows the PFD to operate at a lower frequency than the reference clock.
The overall divide ratio inside the loop is the product of the Pre-Scale and M dividers (P*M). The 5-bit pll_cp_adj
is to set the charge pump current from 0 to 1.55mA with a step of 50µA. In nominal condition, if vco runs at 5GHz
with P-ratio and M-ratio set as 2 and 4, the DACCLK frequency would be 2.5GHz and PFD frequency 625MHz.
This needs 600µA charge pump current to stabilize the loop and gives the optimized phase noise performance.
When P*M ratio increases, the charge pump current needs to be increased accordingly to sustain enough phase
margin for the loop. By tuning the charge pump current, a wide range of PM ratio can be supported with the
internal loop filter. In very extreme cases when the P*M ratio is huge (ex. PFD frequency of 10MHz, VCO
frequency of 4GHz) and the loop cannot be stabilized even with the largest charge pump current, an external
loop filter is required.
7.4.2 PRBS Test Mode
The DAC37J82 and DAC38J82 support three types of PRBS sequences (2⁷-1, 2²³-1, and 2³¹-1) to verify the
SerDes via SIF. To run the PRBS test on the DAC, users first need to setup the DAC for normal use, then make
the following SPI writes:
1. config74, set bits 4:0 to 0x1E to disable JESD clock.
2. config61, set bits 14:12 to 0x2 to enable the 7-bit PRBS test pattern; or set bits 14:12 to 0x3 to enable the
23-bit PRBS test pattern; or set bits 14:12 to 0x4 to enable the 31-bit PRBS test pattern.
3. config27, set bits 11:8 to 0x3 to output PRBS testfail on ALARM pin.
4. config27, set bits 14:12 to the lane to be tested (0 through 7).
5. config62, make sure bits 12:11 are set to 0x0 to disable character alignment.
Users should monitor the ALARM pin to see the results of the test. If the test is failing, ALARM will be high (or
toggling if marginal). If the test is passing, the ALARM will be low.
7.5 Register Map
58
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