DAC38J82_15 Datasheet, PDF (53/119 Pages) Texas Instruments – DAC3xJ82 Dual-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface

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DAC37J82, DAC38J82
SLASE16B – JANUARY 2014 – REVISED MAY 2014
– FIFO write error. Occurs if write request and FIFO is full.
– FIFO write full: Occurs if FIFO is full.
– FIFO read error. Occurs if read request and FIFO is empty.
– FIFO read empty: Occurs if FIFO is empty.
– alarm_rw0_pll. Occurs if the PLL in the SerDes block R0 goes out of clock.
– alarm_rw1_pll. Occurs if the PLL in the SerDes block R0 goes out of clock.
• SYSREF alarm
– alarm_sysref_err. Occurs when the SYSREF is received at an unexpected time. If too many of these
occur it will cause the JESD to go into synchronization mode again.
• DAC PLL alarm
– alarm_from_pll. Occurs when the DAC PLL is out of lock.
• PAP alarms
– alarm_pap. Occurs when the average power is above the threshold. While any alarm_pap is asserted the
attenuation for the appropriate data path is applied.
7.3.25 LVPECL Inputs
Figure 75 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the SYSREF (SYSREFP/N).
LMK04828
LVPECL Driver
DCLK and SYSREF Receiver
0.01 µF
C_AC
100 O
240 O
240 O
0.01 µF
100 Oresistor
is internal
Figure 75. DACCLKP/N and SYSREFP/N Equivalent Input Circuit
7.3.26 CMOS Digital Inputs
Figure 76 shows a schematic of the equivalent CMOS digital inputs of the DAC37J82/DAC38J82. SDIO, SCLK,
TCLK, SLEEP, TESTMODE and TXENABLE have pull-down resistors while SDENB, RESETB, TMS, TDI and
TRSTB have pull-up resistors internal to the DAC37J82/DAC38J82. See the specification table for logic
thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ.
IOVDD
IOVDD
SDIO
SCLK
TCLK
SLEEP
TXENABLE
TESTMODE
100 k
400
internal
digital in
100 k
SDENB
RESETB
TMS
TDI
TRSTB
400
internal
digital in
GND
GND
Figure 76. CMOS Digital Equivalent Input
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