DAC38J82_15 Datasheet, PDF (107/119 Pages) Texas Instruments – DAC3xJ82 Dual-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface

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8.2.2.3 Application Performance Plots
DAC37J82, DAC38J82
SLASE16B – JANUARY 2014 – REVISED MAY 2014
Ref -15.2 dBm
-20
1 RM * -30
CLRWR
-40
-50
-60
-70
-80
-90
-100
-110
Center 1.8 GHz
* Att 15 dB
* RBW 100 kHz
* VBW 1 MHz
* SWT 2 s
100 MHz/
A
NOR
3DB
Span 1 GHz
Figure 85. 192MHz Wideband 256QAM Signal Spectrum
Ref -15.6 dBm
-20
-30
-40
1 RM * -50
CLRWR
-60
-70
-80
-90
-100
-110
Center 1.8 GHz
Tx Channel
Bandwidth
Adjacent Channel
Bandwidth
Spacing
Alternate Channel
Bandwidth
Spacing
* Att 15 dB
* RBW 100 kHz
* VBW 1 MHz
* SWT 2 s
A
100.0103901 MHz/
192 MHz
192 MHz
200 MHz
192 MHz
400 MHz
Power
Lower
Upper
Lower
Upper
NOR
3DB
Span 1.000103901 GHz
E-UTRA/LTE Square
-2.54 dBm
-64.41 dB
-63.42 dB
-66.38 dB
-65.18 dB
Figure 86. 192MHz Wideband 256QAM Signal ACPR
8.3 Initialization Set Up
The following start up sequence is recommended to power up the DAC38J82/DAC37J82 family.
1. Set TXENABLE low.
2. Supply all 0.9-V supplies (VDDDIG09, VDDT09, VDDDAC09, VDDCLK09), all 1.8-V supplies (VDDR18,
VDDS18, VQPS18, VDDIO18, VDDAPLL18, VDDAREF18), and all 3.3-V supplies (VDDADAC33). The
supplies can be powered up simultaneously or in any order. There are no specific requirements on the ramp
rate for the supplies.
3. RESET the JTAG port by either toggling TRSTB low if using the JTAG port or holding TRSTB low if not using
JTAG.
4. Start the DACCLK generation.
5. Toggle RESETB low to reset the SIF registers.
6. Program the DAC PLL settings (config26, config49, config50, config51). If the PLL is not used, set pll_sleep
and pll_reset to “1” and pll_ena to “0”.
7. Program the SERDES settings (config61, config62) including the serdes_clk_sel and serdes_refclk_div.
8. Program the SERDES lane settings (config63, config71, config73, config74, config96).
9. Program clkjesd_div, cdrvser_sysref_mode, and interp.
10. Program the JESD settings (config3, config74-77, config79, config80-85, config92, config97).
11. Program the DIG block settings (NCO, PA protection, QMC, fractional delay, etc.) and set the preferred
SYNC modes for the digital blocks (config30-32).
12. Verify the SERDES PLL lock status by checking the SERDES PLL alarms: alarm_rw0_pll (alarm for lanes 0
through 3) and alarm_rw1_pll (alarm for lanes 4 through 7).
13. Set init_state to “0000” and jesd_reset_n to “1” to start the JESD204B link initialization.
14. Start the SYSREF generation.
15. Enable transmission of data by asserting the TXENABLE pin or setting sif_txenable to “1”.
16. Clear the alarms, then wait approximately 1-2µs and check values.
17. Verify that DAC output is the desired output.
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DAC37J82 DAC38J82
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