DAC38J82_15 Datasheet, PDF (46/119 Pages) Texas Instruments – DAC3xJ82 Dual-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface

DAC37J82, DAC38J82
SLASE16B – JANUARY 2014 – REVISED MAY 2014
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16
+
D
-
|x|
16
Input
12
N=64 or 128
16
N
Divide &
round
|x|
>>
16
Output
16
10
mem_pap_vth
1
mem_pap_gain
Figure 74. Diagram of Power Measurement and PA Protection Mechanism
7.3.19 Serdes Test Modes
The DAC37J82/DAC38J82 supports a number of basic pattern generation and verification of SerDes via SIF.
Three pseudo random bit stream (PRBS) sequences are available, along with an alternating 0/1 pattern and a
20-bit user-defined sequence. The 2⁷-1,2³¹-1 or 2²³-1 sequences implemented can often be found programmed
into standard test equipment, such as a Bit Error Rate Tester (BERT). Pattern generation and verification
selection is via the TESTPATT fields of rw_cfgrx0[14:12], as shown in Table 18.
Table 18. SerDes Test Pattern Selection
TESTPATT
000
001
010
011
100
101
11x
EFFECT
Test mode disabled.
Alternating 0/1 Pattern. An alternating 0/1 pattern with a period of 2UI.
Generate or Verify 2⁷-1 PRBS. Uses a 7-bit LFSR with feedback polynomial x⁷ + x⁶ + 1.
Generate or Verify 2²³ -1 PRBS. Uses an ITU O.150 conformant 23-bit LFSR with feedback polynomial x²³ + x¹⁸ + 1.
Generate or Verify 2³¹-1 PRBS. Uses an ITU O.150 conformant 31-bit LFSR with feedback polynomial x³¹ + x²⁸ + 1.
User-defined 20-bit pattern. Uses the USR PATT IEEE1500 Tuning instruction field to specify the pattern. The default value
is 0x66666.
Reserved
Pattern verification compares the output of the serial to parallel converter with an expected pattern. When there
is a mismatch, the TESTFAIL bit is driven high, which can be programmed to come out the ALARM pin by
setting dtest[3:0] to “0011”.
The DAC37J82/DAC38J82 also provide a number of advanced diagnostic capabilities controlled by the IEEE
1500 interface. These are:
• Accumulation of pattern verification errors;
• The ability to map out the width and height of the receive eye, known as Eye Scan;
• Real-time monitoring of internal voltages and currents;
The SerDes blocks support the following IEEE1500 instructions:
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