TMS320C6671_15 Datasheet, PDF (91/238 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6671
Fixed and Floating-Point Digital Signal Processor
SPRS756E—March 2014
Table 3-20 Reset Mux Register (RSTMUXx) Field Descriptions
Bit
31-10
9
Field
Reserved
EVTSTATCLR
8
Reserved
7-5 DELAY
4
EVTSTAT
3-1 OMODE
0
LOCK
End of Table 3-20
Description
Reserved
Clear event status
0 = Writing 0 has no effect
1 = Writing 1 to this bit clears the EVTSTAT bit
Reserved
Delay cycles between NMI & local reset
000b = 256 CPU/6 cycles delay between NMI & local reset, when OMODE = 100b
001b = 512 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
010b = 1024 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
011b = 2048 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
100b = 4096 CPU/6 cycles delay between NMI & local reset, when OMODE=100b (Default)
101b = 8192 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
110b = 16384 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
111b = 32768 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
Event status.
0 = No event received (Default)
1 = WD timer event received by Reset Mux block
Timer event operation mode
000b = WD timer event input to the reset mux block does not cause any output event (default)
001b = Reserved
010b = WD timer event input to the reset mux block causes local reset input to CorePac
011b = WD timer event input to the reset mux block causes NMI input to CorePac
100b = WD timer event input to the reset mux block causes NMI input followed by local reset input to CorePac. Delay
between NMI and local reset is set in DELAY bit field.
101b = WD timer event input to the reset mux block causes device reset to C6671
110b = Reserved
111b = Reserved
Lock register fields
0 = Register fields are not locked (default)
1 = Register fields are locked until the next timer reset
3.3.20 DSP Suspension Control Register (DSP_SUSP_CTL)
The DSP Suspension Control Register controls the emulation suspension signals from DSP cores. The DSP
Suspension Control Register is shown in Figure 3-19 and described in Table 3-21.
Figure 3-19 DSP Suspension Control Register (DSP_SUSP_CTL)
31
30
0
DSP_SUSP_CTL
Reserved
R/W-0
R-0
Legend: R = Read only; RW = Read/Write; -n = value after reset
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Device Configuration 91