TMS320C6671_15 Datasheet, PDF (116/238 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6671
Fixed and Floating-Point Digital Signal Processor
SPRS756E—March 2014
6.4 Power Supply to Peripheral I/O Mapping
Table 6-4
Power Supply to Peripheral I/O Mapping ^{(1) (2)}
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
Power Supply
CVDD Supply Core Voltage
DVDD15 1.5-V supply I/O voltage
I/O Buffer Type
LJCB
DDR3 (1.5 V)
Associated Peripheral
CORECLK(P|N) PLL input buffers
SRIOSGMIICLK(P|N) SerDes PLL input buffers
DDRCLK(P|N) PLL input buffers
PCIECLK(P|N) SerDes PLL input buffers
MCMCLK(P|N) SerDes PLL input buffers
PASSCLK(P|N) PLL input buffers
All DDR3 memory controller peripheral I/O buffers
DVDD18 1.8-V supply I/O voltage
VDDT1
VDDT2
Hyperlink SerDes termination and analog front-end supply
SRIO/SGMII/PCIE SerDes termination and analog front-end
supply
LVCMOS (1.8 V)
Open-drain (1.8V)
SerDes/CML
All GPIO peripheral I/O buffers
All JTAG and EMU peripheral I/O buffers
All Timer peripheral I/O buffers
All SPI peripheral I/O buffers
All RESETs, NMI, Control peripheral I/O buffers
All Hyperlink sideband peripheral I/O buffers
All MDIO peripheral I/O buffers
All UART peripheral I/O buffers
All TSIP0 and TSIP1 peripheral I/O buffers
All EMIF16 peripheral I/O buffers
All I²C peripheral I/O buffers
All SmartReflex peripheral I/O buffers
Hyperlink SerDes CML IO buffers
SerDes/CML
SRIO/SGMII/PCIE SerDes CML IO buffers
End of Table 6-4
1 Note that this table does not attempt to describe all functions of all power supply terminals, but only those whose purpose it is to power peripheral I/O buffers and clock
input buffers.
2 See the Hardware Design Guide for KeyStone I Devices in ‘‘Related Documentation from Texas Instruments’’ on page 72 for more information about individual peripheral I/O.
116 Device Operating Conditions
Copyright 2014 Texas Instruments Incorporated
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