TMS320C6671_15 Datasheet, PDF (152/238 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6671
Fixed and Floating-Point Digital Signal Processor
SPRS756E—March 2014
7.7.4 DDR3 PLL Input Clock Electrical Data/Timing
Table 7-29 DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements
(see Figure 7-26 and Figure 7-22)
No.
1 tc(DDRCLKN)
1 tc(DDRCLKP)
3 tw(DDRCLKN)
2 tw(DDRCLKN)
2 tw(DDRCLKP)
3 tw(DDRCLKP)
4 tr(DDRCLK_250mv)
4 tf(DDRCLK_250mv)
5 tj(DDRCLKN)
5 tj(DDRCLKP)
End of Table 7-29
DDRCLK[P:N]
Cycle time _ DDRCLKN cycle time
Cycle time _ DDRCLKP cycle time
Pulse width _ DDRCLKN high
Pulse width _ DDRCLKN low
Pulse width _ DDRCLKP high
Pulse width _ DDRCLKP low
Transition time _ DDRCLK differential rise time (250 mV)
Transition time _ DDRCLK differential fall time (250 mV)
Jitter, peak_to_peak _ periodic DDRCLKN
Jitter, peak_to_peak _ periodic DDRCLKP
Figure 7-26 DDR3 PLL DDRCLK Timing
DDRCLKN
DDRCLKP
1
2
4
Min
Max Unit
3.2
25 ns
3.2
25 ns
0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN) ns
0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN) ns
0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP) ns
0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP) ns
50
350 ps
50
350 ps
0.02*tc(DDRCLKN) ps
0.02*tc(DDRCLKP) ps
3
5
152 Peripheral Information and Electrical Specifications
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