TLK2201 Datasheet, PDF (9/19 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK2201, TLK2201I
ETHERNET TRANSCEIVERS
SLLS420C – JUNE 2000 – REVISED NOVEMBER 2001
Terminal Functions (Continued)
TERMINAL
NAME
NO.
SIGNAL (Continued)
RBCMODE
32
SYNCEN
24
SYNC/PASS
47
LOS
26
MODESEL
15
TEST
LOOPEN
19
TCK
49
JTDI
48
JTDO
27
JTRSTN
56
JTMS
55
ENABLE
28
PRBSEN
16
TESTEN
17
POWER
VDD
5, 10, 20,
23, 29, 37,
42, 50, 63
VDDA
53, 57, 59,
60
VDDPLL
18
† _{P/D = Internal pulldown}
‡ _{P/U = Internal pullup}
I/O
DESCRIPTION
I
P/D^†
I
P/U^‡
O
O
I
P/D^†
Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output on
RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on
RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate clock is
output on RBC0 and RBC1 is held low.
Synchronous function enable. When SYNCEN is high, the internal synchronization function is activated.
When this function is activated, the transceiver detects the K28.5 comma character (0011111 negative
beginning disparity) in the serial data stream and realigns data on byte boundaries if required. When
SYNCEN is low, serial input data is unframed in RD0 – RD9.
Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in the serial
data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In PRBS test mode
(PRBSEN=high), SYNC/PASS outputs the status of the PRBS test results (high=pass).
Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.
If magnitude of RXP–RXN > 150 mV, LOS = 1, valid input signal
If magnitude of RXP–RXN < 150 mV and > 50 mV, LOS is undefined
If magnitude of RXP–RXN < 50 mV, LOS = 0, loss of signal
Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface. When
low the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected. The default
mode is the TBI.
I
P/D^†
I
I
P/U^‡
O
I
P/U^‡
I
P/U^‡
I
P/U^‡
I
P/D^†
I
P/D^†
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted
serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction
with the protocol device. The TXP and TXN outputs are held in a high-impedance state during the
loop-back test. LOOPEN is held low during standard operational state with external serial outputs and
inputs active.
Test clock. IEEE1149.1 (JTAG)
Test data input. IEEE1149.1 (JTAG)
Test data output. IEEE1149.1 (JTAG)
Reset signal. IEEE1149.1 (JTAG)
Test mode select. IEEE1149.1 (JTAG)
When this terminal is low, the device is disabled for Iddq testing. RD0 – RD9, RBCn, TXP, and TXN are
high impedance. The pullup and pulldown resistors on any input are disabled. When ENABLE is high, the
device operates normally.
PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS verification
circuit in the receive side is also enabled. A PRBS signal can be fed to the receive inputs and checked for
errors, that are reported by the SYNC/PASS terminal indicating low.
Manufacturing test terminal
Supply Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
Supply Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter
Supply PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
9