TLK2201 Datasheet, PDF (12/19 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK2201, TLK2201I
ETHERNET TRANSCEIVERS
SLLS420C – JUNE 2000 – REVISED NOVEMBER 2001
transmitter/receiver characteristics
PARAMETER
Vod = |TxD–TxN|
V(cm)
Ilkg(R)
CI
t(TJ)
Transmit common mode voltage range
Receiver Input voltage requirement,
Vid = |RxP – RxN|
Receiver common mode voltage range,
(RxP + RxN)/2
Receiver input leakage current
Receiver input capacitance
Serial data total jitter (peak-to-peak)
t(DJ)
Serial data deterministic jitter (peak-to-peak)
tr, tf
td(Tx _latency)
td(Rx _latency)
Differential signal rise, fall time (20% to 80%)
Serial data jitter tolerance minimum required eye
opening, (per IEEE-802.3 specification)
Receiver data acquisition lock time from powerup
Data relock time from loss of synchronization
Tx latency
TBI modes
DDR mode
Rx latency
TBI modes
DDR mode
TX+
tr
TX–
tf
80%
VOD
20%
80%
50%
20%
tf
80%
50%
20%
tr
0V
∼V
∼V
∼V
∼V
∼ 1V
∼ –1V
TEST CONDITIONS
Rt = 50 Ω
Rt = 75 Ω
Rt = 50 Ω
Rt = 75 Ω
Differential output jitter, Random
+ deterministic, PRBS pattern,
R_ω = 125 MHz
Differential output jitter, PRBS
pattern,
R_ω = 125 MHz
RL = 50 Ω,
CL = 5 pF,
See Figures 7 and 8
Differential input jitter, Random
+ deterministic, R_ω = 125 MHz
See Figure 1
See Figure 6
CL
5 pF
CL
5 pF
MIN
600
800
1000
1000
TYP
850
1050
1250
1250
MAX
1100
1200
1400
1400
200
1600
UNIT
mV
mV
mV
1000 1250 2250
mV
–350
350
µA
2
pF
0.24
UI
0.12
UI
100
250
ps
0.25
UI
500
µs
1024 Bit times
19
20
UI
29
30
21
31
27
34
UI
50 Ω
50 Ω
Figure 7. Differential and Common-Mode
Output Voltage Definitions
CLOCK
Figure 8. Transmitter Test Setup
1.4 V
tr
tf
DATA
tr
80%
50%
20%
tf
2V
0.8 V
Figure 9. TTL Data I/O Valid Levels for AC Measurement
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