TLK2201 Datasheet, PDF (8/19 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK2201, TLK2201I
ETHERNET TRANSCEIVERS
SLLS420C – JUNE 2000 – REVISED NOVEMBER 2001
PRBS function
These devices have a built-in 2⁷–1 PRBS function. When the PRBSEN control bit is set high, the PRBS test
is enabled. A PRBS is generated and fed into the 10-bit parallel transmitter input bus. Data from the normal
parallel input source is ignored during PRBS test mode. The PRBS pattern is then fed through the transmit
circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a (BERT) bit error
rate tester or to the receiver of another TLK2201 or TLK2201I. Since the PRBS is not really random and is really
a predetermined sequence of ones and zeros, the data can be captured and checked for errors by a BERT.
These devices also have a built-in BERT function on the receiver side that is enabled by PRBSEN. It can receive
a PRBS pattern and check for errors, and then reports the errors by forcing the SYNC/PASS terminal low. When
PRBS is enabled, RBCMODE and MODESEL are ignored. The device operates in TBI mode with a full-rate
clock on RBC0. The PRBS testing supports two modes (normal and latched), which are controlled by the
SYNCEN input. When SYNCEN is low, the result of the PRBS bit error rate test is passed to the SYNC/PASS
terminal. When SYNCEN is high the result of the PRBS verification is latched on the SYNC/PASS output (i.e.,
a single failure forces SYNC/PASS to remain low).
Terminal Functions
TERMINAL
NAME
NO.
SIGNAL
TXP
62
TXN
61
RXP
54
RXN
52
REFCLK
22
TD0–TD9
2–4, 6–9,
11–13
RD0–RD9
45, 44, 43,
41, 40, 39,
38, 36, 35,
34
RBC0
31
RBC1
30
I/O
DESCRIPTION
PECL
O
PECL
I
I
I
O
O
Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper or an
optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high and are active
when LOOPEN is low.
Differential input receive. RXP and RXN together are the differential serial input interface from a copper
or an optical I/F module.
Reference clock. REFCLK is an external input clock that synchronizes the receiver and transmitter
interface (100 MHz to 160 MHz). The transmitter uses this clock to register the input data (TD0–TD9)
for serialization.
In the TBI mode that data is registered on the rising edge of REFCLK.
In the DDR mode, the data is registered on both the rising and falling edges of REFCLK with the most
significant bits aligned to the rising edge of REFCLK.
Transmit data. When in the TBI mode (MODESEL = low) these inputs carry 10-bit parallel data output
from a protocol device to the transceiver for serialization and transmission. This 10-bit parallel data is
clocked into the transceiver on the rising edge of REFCLK and transmitted as a serial stream with TD0
sent as the first bit.
When in the DDR mode (MODESEL = high) only TD0–TD4 are valid. The 5-bit parallel data is clocked
into the transceiver on the rising and falling edge of REFCLK and transmitted as a serial stream with TD0
sent as the first bit.
Receive data. When in TBI mode (MODESEL = low) these outputs carry 10-bit parallel data output from
the transceiver to the protocol layer. The data is referenced to terminals RBC0 and RBC1, depending
on the receive clock mode selected. RD0 is the first bit received.
When in the DDR mode (MODESEL = high) only RD0–RD4 are valid. RD5–RD9 are held low. The 5-bit
parallel data is clocked out of the transceiver on the rising edge of RBC0.
Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit output data
on RD0–RD9. The operation of these clocks is dependent upon the receive clock mode selected.
In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and RBC1.
These clocks are adjusted to half-word boundaries in conjunction with synchronous detect. The clocks
are always expanded during data realignment and never slivered or truncated. RBC0 registers bytes
1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.
In the normal rate mode, only RBC0 is valid and operates at 1/10 the serial data rate. Data is aligned
to the rising edge.
In the DDR mode, only RBC0 is valid and operates at 1/10 the serial data rate. Data is aligned to both
the rising and falling edges.
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