TLK2201 Datasheet, PDF (7/19 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK2201, TLK2201I
ETHERNET TRANSCEIVERS
SLLS420C – JUNE 2000 – REVISED NOVEMBER 2001
data reception latency
The serial to parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The minimum latency in TBI mode is 21 bit times and the
maximum latency is 31 bit times. The minimum latency in DDR mode is 27 bit times and maximum latency is
34 bit times.
data reception latency (continued)
RXP, RXN
RD(0–9)
10 Bit Code
td(Rx _latency)
10 Bit Code
RBC0
Figure 6. Receiver Latency – TBI Normal Mode Shown
loss of signal detection
These devices have a loss of signal (LOS) detection circuit for conditions where the incoming signal no longer
has sufficient voltage level to keep the clock recovery circuit in lock. The LOS is intended to be an indication
of gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication
of signal coding health. Under a PRBS serial input pattern, LOS is high for signal amplitudes greater than
150 mV. The LOS is low for all amplitudes below 50 mV. Between 50 mV and 150 mV, LOS is undetermined.
testability
The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable
function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also
allows for a BIST( built-in self test). The terminal setting, TESTEN high, enables the test mode. The terminal
TESTEN has an internal pulldown resistor, so it defaults to normal operation. The TESTEN is only used for
factory testing, and is not intended for the end-user.
loopback testing
The transceiver can provide a self-test function by enabling (LOOPEN to high level) the internal loopback path.
Enabling this function causes serial transmitted data to be routed internally to the receiver. The parallel data
output can be compared to the parallel input data for functional verification. (The external differential output is
held in a high-impedance state during the loopback testing.)
enable function
When held low, ENABLE disables all quiescent power in both the analog and digital circuitry. This allows an
ultralow-power idle state when the link is not active.
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