TLK2201 Datasheet, PDF (5/19 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

receiver clock select mode (continued)
TLK2201, TLK2201I
ETHERNET TRANSCEIVERS
SLLS420C – JUNE 2000 – REVISED NOVEMBER 2001
RBC0
RBC1
SYNC
RD(0–9)
td(S)
td(S)
td(H)
td(H)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
Figure 2. Synchronous Timing Characteristics Waveforms (TBI half-rate mode)
In the normal-rate mode, only RBC0 is used and operates at full data rate (i.e., 1.25 Gbps data rate produces
a 125 MHz clock). The received data is output with respect to the rising edge of RBC0. RBC1 is low in this mode.
Refer to the timing diagram shown in Figure 3.
RBC0
SYNC
td(S)
td(H)
RD(0–9)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
Figure 3. Synchronous Timing Characteristics Waveforms (TBI full-rate mode)
In the double data rate mode, the receiver presents the data on both the rising and falling edges of RBC0. RBC1
is low impedance. The data is clocked bit-0 first, and aligned to the rising edge of RBC0. Refer to the timing
diagram shown in Figure 4.
RBC0
SYNC
td(S)
td(H)
td(S)
td(H)
RD(0–4)
K28.5 K28.5 DXX.X DXX.X DXX.X DXX.X DXX.X DXX.X K28.5 K28.5 DXX.X
Bits 0–4 Bits 5–9
Figure 4. Synchronous Timing Characteristics Waveforms (DDR mode)
The receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset.
The received serial data rate (RXP and RXN) is at the same baud rate as the transmitted data stream, ±0.02%
(200 PPM) for proper operation (see page 11).
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